mtd_spi_nor.h
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1 /*
2  * Copyright (C) 2016 Eistec AB
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
26 #include <stdint.h>
27 
28 #include "periph_conf.h"
29 #include "periph/spi.h"
30 #include "periph/gpio.h"
31 #include "mtd.h"
32 
33 #ifdef __cplusplus
34 extern "C"
35 {
36 #endif
37 
41 typedef struct {
42  uint8_t rdid;
43  uint8_t wren;
44  uint8_t rdsr;
45  uint8_t wrsr;
46  uint8_t read;
47  uint8_t read_fast;
48  uint8_t page_program;
49  uint8_t sector_erase;
50  uint8_t block_erase_32k;
51  uint8_t block_erase_64k;
52  uint8_t chip_erase;
53  uint8_t sleep;
54  uint8_t wake;
55  /* TODO: enter 4 byte address mode for large memories */
57 
63 typedef struct __attribute__((packed)) {
64  uint8_t bank;
65  uint8_t manuf;
66  uint8_t device[2];
68 
74 #define JEDEC_NEXT_BANK (0x7f)
75 
81 #define JEDEC_BANK_MAX (10)
82 
86 #define SPI_NOR_F_SECT_4K (1)
87 
91 #define SPI_NOR_F_SECT_32K (2)
92 
96 #define SPI_NOR_F_SECT_64K (4)
97 
101 typedef struct {
103  uint32_t wait_chip_erase;
104  uint32_t wait_64k_erase;
105  uint32_t wait_32k_erase;
106  uint32_t wait_sector_erase;
107  uint32_t wait_chip_wake_up;
109  uint16_t flag;
110  spi_t spi;
112  gpio_t cs;
113  gpio_t wp;
114  gpio_t hold;
116 
122 typedef struct {
132  uint32_t page_addr_mask;
138  uint32_t sec_addr_mask;
150  uint8_t sec_addr_shift;
156  uint8_t addr_width;
157 } mtd_spi_nor_t;
158 
162 extern const mtd_desc_t mtd_spi_nor_driver;
163 
164 /* Available opcode tables for known devices */
165 /* Defined in mtd_spi_nor_configs.c */
174 
181 
182 #ifdef __cplusplus
183 }
184 #endif
185 
spi_clk_t
Definition: periph_cpu.h:351
Low-level GPIO peripheral driver interface definitions.
const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default
Default command opcodes.
const mtd_desc_t mtd_spi_nor_driver
NOR flash SPI MTD device operations table.
const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default_4bytes
Default 4-byte addresses opcodes.
spi_mode_t
Support SPI modes.
Definition: periph_cpu.h:42
Low-level SPI peripheral driver interface definition.
MTD driver interface.
Definition: mtd.h:203
MTD device descriptor.
Definition: mtd.h:111
Internal representation of JEDEC memory ID codes.
Definition: mtd_spi_nor.h:63
uint8_t bank
Manufacturer ID bank number, 1 through 10, see JEP106.
Definition: mtd_spi_nor.h:64
uint8_t manuf
Manufacturer ID, 1 byte.
Definition: mtd_spi_nor.h:65
SPI NOR flash opcode table.
Definition: mtd_spi_nor.h:41
uint8_t read_fast
Read data bytes, 3 byte address, at higher speed.
Definition: mtd_spi_nor.h:47
uint8_t wrsr
Write status register.
Definition: mtd_spi_nor.h:45
uint8_t block_erase_32k
32KiB block erase
Definition: mtd_spi_nor.h:50
uint8_t page_program
Page program.
Definition: mtd_spi_nor.h:48
uint8_t read
Read data bytes, 3 byte address.
Definition: mtd_spi_nor.h:46
uint8_t chip_erase
Chip erase.
Definition: mtd_spi_nor.h:52
uint8_t block_erase_64k
Block erase (usually 64 KiB)
Definition: mtd_spi_nor.h:51
uint8_t wake
Release from deep power down.
Definition: mtd_spi_nor.h:54
uint8_t sleep
Deep power down.
Definition: mtd_spi_nor.h:53
uint8_t sector_erase
Block erase 4 KiB.
Definition: mtd_spi_nor.h:49
uint8_t rdid
Read identification (JEDEC ID)
Definition: mtd_spi_nor.h:42
uint8_t wren
Write enable.
Definition: mtd_spi_nor.h:43
uint8_t rdsr
Read status register.
Definition: mtd_spi_nor.h:44
Compile-time parameters for a serial flash device.
Definition: mtd_spi_nor.h:101
uint32_t wait_chip_wake_up
Chip wake up time in µs.
Definition: mtd_spi_nor.h:107
gpio_t hold
HOLD pin GPIO handle.
Definition: mtd_spi_nor.h:114
gpio_t wp
Write Protect pin GPIO handle.
Definition: mtd_spi_nor.h:113
uint16_t flag
Config flags.
Definition: mtd_spi_nor.h:109
spi_clk_t clk
SPI clock.
Definition: mtd_spi_nor.h:108
const mtd_spi_nor_opcode_t * opcode
Opcode table for the device.
Definition: mtd_spi_nor.h:102
spi_t spi
SPI bus the device is connected to.
Definition: mtd_spi_nor.h:110
spi_mode_t mode
SPI mode.
Definition: mtd_spi_nor.h:111
uint32_t wait_sector_erase
4KB sector erase wait time in µs
Definition: mtd_spi_nor.h:106
uint32_t wait_chip_erase
Full chip erase wait time in µs.
Definition: mtd_spi_nor.h:103
gpio_t cs
CS pin GPIO handle.
Definition: mtd_spi_nor.h:112
uint32_t wait_32k_erase
32KB page erase wait time in µs
Definition: mtd_spi_nor.h:105
uint32_t wait_64k_erase
64KB page erase wait time in µs
Definition: mtd_spi_nor.h:104
Device descriptor for serial flash memory devices.
Definition: mtd_spi_nor.h:122
uint32_t page_addr_mask
bitmask to corresponding to the page address
Definition: mtd_spi_nor.h:132
mtd_jedec_id_t jedec_id
JEDEC ID of the chip.
Definition: mtd_spi_nor.h:125
mtd_dev_t base
inherit from mtd_dev_t object
Definition: mtd_spi_nor.h:123
const mtd_spi_nor_params_t * params
SPI NOR params.
Definition: mtd_spi_nor.h:124
uint8_t sec_addr_shift
number of right shifts to get the address to the start of the sector
Definition: mtd_spi_nor.h:150
uint32_t sec_addr_mask
bitmask to corresponding to the sector address
Definition: mtd_spi_nor.h:138
uint8_t page_addr_shift
number of right shifts to get the address to the start of the page
Definition: mtd_spi_nor.h:144
uint8_t addr_width
number of address bytes
Definition: mtd_spi_nor.h:156