cc26xx_cc13xx.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Leon George
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include <stdint.h>
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
28 typedef volatile uint8_t reg8_t;
32 typedef volatile uint16_t reg16_t;
36 typedef volatile uint32_t reg32_t;
37 
41 typedef struct {
44 } reg8_m4_t;
45 
50 
54 typedef struct {
57 } reg32_m16_t;
58 
66 typedef enum IRQn {
67  /****** Cortex-M4 Processor Exceptions Numbers ****************************/
72  BusFault_IRQn = -11,
74  SVCall_IRQn = - 5,
76  PendSV_IRQn = - 2,
77  SysTick_IRQn = - 1,
79  /****** CC13x2 specific Interrupt Numbers *********************************/
81  I2C_IRQN = 1,
83  PKA_IRQN = 3,
85  UART0_IRQN = 5,
87  SSI0_IRQN = 7,
88  SSI1_IRQN = 8,
90  RF_HW_IRQN = 10,
92  I2S_IRQN = 12,
103  CRYPTO_IRQN = 23,
104  UDMA_IRQN = 24,
107  SW0_IRQN = 27,
110  PROG_IRQN = 30,
113  TRNG_IRQN = 33,
114 #ifdef CPU_VARIANT_X2
115  OSC_IRQN = 34,
116  AUX_TIMER2_IRQN = 35,
117  UART1_IRQN = 36,
118  BATMON_IRQN = 37,
120  IRQN_COUNT = (BATMON_IRQN + 1)
121 #else
122  IRQN_COUNT = (TRNG_IRQN + 1)
123 #endif
124 
126 
131 #define __MPU_PRESENT 1
132 #define __NVIC_PRIO_BITS 3
133 #define __Vendor_SysTickConfig 0
136 #define RCOSC48M_FREQ 48000000
137 #define RCOSC24M_FREQ 24000000
142 #ifdef CPU_VARIANT_X2
143 #include <core_cm4.h>
144 #else
145 #include <core_cm3.h>
146 #endif
153 #define FLASH_BASE 0x00000000
154 #define PERIPH_BASE 0x40000000
155 #define PERIPH_BASE_NONBUF 0x60000000
156 #define ROM_HARD_API_BASE 0x10000048
157 #define ROM_API_TABLE ((uint32_t *) 0x10000180)
164 #define ADI_DIR 0x00000000
165 #define ADI_SET 0x00000010
166 #define ADI_CLR 0x00000020
167 #define ADI_MASK4B 0x00000040
168 #define ADI_MASK8B 0x00000060
169 #define ADI_MASK16B 0x00000080
172 #ifdef __cplusplus
173 }
174 #endif
175 
volatile uint32_t reg32_t
Unsigned 32-bit register type.
Definition: cc26xx_cc13xx.h:36
reg16_t reg8_m8_t
Masked 8-bit register.
Definition: cc26xx_cc13xx.h:49
volatile uint16_t reg16_t
Unsigned 16-bit register type.
Definition: cc26xx_cc13xx.h:32
enum IRQn IRQn_Type
Interrupt number definition.
volatile uint8_t reg8_t
Unsigned 8-bit register type.
Definition: cc26xx_cc13xx.h:28
@ PendSV_IRQn
14 Cortex-M4 Pend SV Interrupt
Definition: cc26xx_cc13xx.h:76
@ GPTIMER_0B_IRQN
32 Timer 0 subtimer B
Definition: cc26xx_cc13xx.h:96
@ UART0_IRQN
21 UART0 Rx and Tx
Definition: cc26xx_cc13xx.h:85
@ GPTIMER_2A_IRQN
35 Timer 2 subtimer A
Definition: cc26xx_cc13xx.h:99
@ AUX_ADC_IRQN
48 AUX ADC IRQ
@ GPTIMER_2B_IRQN
36 Timer 2 subtimer B
@ RF_CPE1_IRQN
18 RF Command and Packet Engine 1
Definition: cc26xx_cc13xx.h:82
@ AON_AUX_SWEV0_IRQN
22 Sensor Controller software event 0, through AON domain
Definition: cc26xx_cc13xx.h:86
@ GPTIMER_0A_IRQN
31 Timer 0 subtimer A
Definition: cc26xx_cc13xx.h:95
@ AUX_COMBO_IRQN
44 AUX combined event, directly to MCU domain
@ WATCHDOG_IRQN
30 Watchdog timer
Definition: cc26xx_cc13xx.h:94
@ MemoryManagement_IRQn
4 Cortex-M4 Memory Management Interrupt
Definition: cc26xx_cc13xx.h:71
@ AON_RTC_IRQN
20 AON RTC
Definition: cc26xx_cc13xx.h:84
@ PROG_IRQN
46 Dynamic Programmable interrupt (default source: PRCM)
@ GPTIMER_3A_IRQN
37 Timer 3 subtimer A
@ IRQN_COUNT
Number of peripheral IDs.
@ I2S_IRQN
28 I2S
Definition: cc26xx_cc13xx.h:92
@ SVCall_IRQn
11 Cortex-M4 SV Call Interrupt
Definition: cc26xx_cc13xx.h:74
@ FLASH_CTRL_IRQN
42 Flash controller
@ GPTIMER_3B_IRQN
38 Timer 3 subtimer B
@ UDMA_ERR_IRQN
41 uDMA Error
@ UsageFault_IRQn
6 Cortex-M4 Usage Fault Interrupt
Definition: cc26xx_cc13xx.h:73
@ SSI1_IRQN
24 SSI1 Rx and Tx
Definition: cc26xx_cc13xx.h:88
@ SysTick_IRQn
15 Cortex-M4 System Tick Interrupt
Definition: cc26xx_cc13xx.h:77
@ ResetHandler_IRQn
1 Reset Handler
Definition: cc26xx_cc13xx.h:68
@ AUX_COMPA_IRQN
47 AUX Comparator A
@ BusFault_IRQn
5 Cortex-M4 Bus Fault Interrupt
Definition: cc26xx_cc13xx.h:72
@ I2C_IRQN
17 I2C
Definition: cc26xx_cc13xx.h:81
@ RF_HW_IRQN
26 RF Core Hardware
Definition: cc26xx_cc13xx.h:90
@ DebugMonitor_IRQn
12 Cortex-M4 Debug Monitor Interrupt
Definition: cc26xx_cc13xx.h:75
@ RF_CPE0_IRQN
25 RF Command and Packet Engine 0
Definition: cc26xx_cc13xx.h:89
@ RF_CMD_ACK_IRQN
27 RF Core Command Acknowledge
Definition: cc26xx_cc13xx.h:91
@ UDMA_IRQN
40 uDMA Software
@ EDGE_DETECT_IRQN
16 AON edge detect
Definition: cc26xx_cc13xx.h:80
@ PKA_IRQN
19 PKA interrupt
Definition: cc26xx_cc13xx.h:83
@ SW0_IRQN
43 Software Event 0
@ HardFault_IRQn
3 Cortex-M4 Hard Fault Interrupt
Definition: cc26xx_cc13xx.h:70
@ GPTIMER_1B_IRQN
34 Timer 1 subtimer B
Definition: cc26xx_cc13xx.h:98
@ CRYPTO_IRQN
39 Crypto Core Result available
@ GPTIMER_1A_IRQN
33 Timer 1 subtimer A
Definition: cc26xx_cc13xx.h:97
@ AON_PRG0_IRQN
45 AON programmable 0
@ SSI0_IRQN
23 SSI0 Rx and Tx
Definition: cc26xx_cc13xx.h:87
@ NonMaskableInt_IRQn
2 Non Maskable Interrupt
Definition: cc26xx_cc13xx.h:69
@ AON_AUX_SWEV1_IRQN
29 Sensor Controller software event 1, through AON domain
Definition: cc26xx_cc13xx.h:93
@ TRNG_IRQN
49 TRNG event
IRQn
Interrupt Number Definition.
Definition: cc2538.h:31
Masked 32-bit register.
Definition: cc26xx_cc13xx.h:54
reg32_t HIGH
High 16-bit half.
Definition: cc26xx_cc13xx.h:56
reg32_t LOW
Low 16-bit half.
Definition: cc26xx_cc13xx.h:55
Masked 8-bit register.
Definition: cc26xx_cc13xx.h:41
reg8_t HIGH
High 4-bit half.
Definition: cc26xx_cc13xx.h:43
reg8_t LOW
Low 4-bit half.
Definition: cc26xx_cc13xx.h:42