cc2538_ssi.h
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1 /*
2  * SPDX-FileCopyrightText: 2014 Loci Controls Inc.
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include "cc2538.h"
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
28 typedef struct {
29  cc2538_reg_t CR0;
30  cc2538_reg_t CR1;
31  cc2538_reg_t DR;
32  cc2538_reg_t SR;
33  cc2538_reg_t CPSR;
34  cc2538_reg_t IM;
35  cc2538_reg_t RIS;
36  cc2538_reg_t MIS;
37  cc2538_reg_t ICR;
38  cc2538_reg_t DMACTL;
39  cc2538_reg_t CC;
40 } cc2538_ssi_t;
41 
45 #define SSI_CR0_DSS(x) (x - 1)
46 
51 #define SSI_CC_CS_SYSDIV (0x0)
52 #define SSI_CC_CS_IODIV (0x1)
53 #define SSI_CC_CS_DSEN (0x4)
56 #ifdef __cplusplus
57 } /* end extern "C" */
58 #endif
59 
cc2538.h
CC2538 MCU interrupt and register definitions.
cc2538_reg_t
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition: cc2538.h:120
cc2538_ssi_t
SSI component registers.
Definition: cc2538_ssi.h:28
cc2538_ssi_t::CR1
cc2538_reg_t CR1
SSI Control Register 1.
Definition: cc2538_ssi.h:30
cc2538_ssi_t::RIS
cc2538_reg_t RIS
SSI Raw Interrupt Status register.
Definition: cc2538_ssi.h:35
cc2538_ssi_t::CPSR
cc2538_reg_t CPSR
SSI Clock Register.
Definition: cc2538_ssi.h:33
cc2538_ssi_t::SR
cc2538_reg_t SR
SSI FIFO/busy Status Register.
Definition: cc2538_ssi.h:32
cc2538_ssi_t::DMACTL
cc2538_reg_t DMACTL
SSI uDMA Control Register.
Definition: cc2538_ssi.h:38
cc2538_ssi_t::CR0
cc2538_reg_t CR0
SSI Control Register 0.
Definition: cc2538_ssi.h:29
cc2538_ssi_t::DR
cc2538_reg_t DR
SSI Data register.
Definition: cc2538_ssi.h:31
cc2538_ssi_t::ICR
cc2538_reg_t ICR
SSI Interrupt Clear Register.
Definition: cc2538_ssi.h:37
cc2538_ssi_t::CC
cc2538_reg_t CC
SSI clock configuration.
Definition: cc2538_ssi.h:39
cc2538_ssi_t::MIS
cc2538_reg_t MIS
SSI Masked Interrupt Status register.
Definition: cc2538_ssi.h:36
cc2538_ssi_t::IM
cc2538_reg_t IM
SSI Interrupt Mask register.
Definition: cc2538_ssi.h:34