92 #define DMA_CHAN_CONFIG_UNSUPPORTED  (UINT8_MAX) 
   98 #define DMA_INC_SRC_ADDR  (0x04)     
   99 #define DMA_INC_DST_ADDR  (0x08)     
  100 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)  
  107 #define DMA_DATA_WIDTH_BYTE      (0x00)  
  108 #define DMA_DATA_WIDTH_HALF_WORD (0x01)  
  109 #define DMA_DATA_WIDTH_WORD      (0x02)  
  112 #ifdef MODULE_PERIPH_DMA 
  116 #define DMA_STREAM_UNDEF (UINT_MAX) 
  139 int dma_transfer(
dma_t dma, 
int chan, 
const volatile void *src, 
volatile void *dst, 
size_t len,
 
  147 void dma_acquire(
dma_t dma);
 
  154 void dma_release(
dma_t dma);
 
  173 uint16_t dma_suspend(
dma_t dma);
 
  181 void dma_resume(
dma_t dma, uint16_t remaining);
 
  188 void dma_stop(
dma_t dma);
 
  210 int dma_configure(
dma_t dma, 
int chan, 
const volatile void *src, 
volatile void *dst, 
size_t len,
 
  228                uint8_t width, 
bool inc_periph);
 
dma_burst_t
Burst Transfer modes for F2/F4/F7.
 
@ DMA_BURST_INCR4
incremental burst of 4 beats
 
@ DMA_BURST_INCR8
incremental burst of 8 beats
 
@ DMA_BURST_SINGLE
single transfer
 
@ DMA_BURST_INCR16
incremental burst of 16 beats
 
dma_fifo_thresh_t
Threshold selection in FIFO mode for F2/F4F7.
 
@ DMA_FIFO_FULL_3_4
3/4 full FIFO
 
@ DMA_FIFO_FULL_1_4
1/4 full FIFO
 
@ DMA_FIFO_FULL_1_2
1/2 full FIFO
 
@ DMA_FIFO_FULL
Full FIFO.
 
@ DMA_PERIPH_TO_MEM
Peripheral to memory.
 
@ DMA_MEM_TO_PERIPH
Memory to peripheral.
 
@ DMA_MEM_TO_MEM
Memory to memory.
 
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
 
void dma_init(void)
Initialize DMA.
 
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
 
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
 
unsigned dma_t
DMA channel type.
 
void dma_start(dma_t dma)
Start a DMA transfer.
 
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7: