Data Structures | Macros | Variables
periph_cpu.h File Reference
CPU » Atmel SAML21

CPU specific definitions for internal peripheral handling. More...

Detailed Description

CPU specific definitions for internal peripheral handling.

CPU specific definitions for internal peripheral handling

Author
Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de

Definition in file periph_cpu.h.

#include "periph_cpu_common.h"
+ Include dependency graph for periph_cpu.h:

Go to the source code of this file.

Data Structures

struct  sam0_aux_cfg_mapping
 NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on. More...
 

Macros

#define PM_BLOCKER_INITIAL   { 0, 0, 0 }
 Override the default initial PM blocker All peripheral drivers ensure required pm modes are blocked.
 
#define DAC_RES_BITS   (12)
 The MCU has a 12 bit DAC.
 
#define DAC_NUMOF   (2)
 The MCU has two DAC outputs.
 

Variables

static const gpio_t sam0_adc_pins [1][20]
 Pins that can be used for ADC input. More...
 
#define CPU_BACKUP_RAM_NOT_RETAINED   (1)
 The Low Power SRAM is not retained during deep sleep.
 

Power mode configuration

#define PM_NUM_MODES   (3)
 
#define SAML21_PM_MODE_BACKUP   (0)
 Wakeup by some IRQs possible, but no RAM retention.
 
#define SAML21_PM_MODE_STANDBY   (1)
 Just peripherals clocked by 32K OSC are active.
 
#define SAML21_PM_MODE_IDLE   (2)
 CPU sleeping, peripherals are active.
 

Peripheral power mode requirements

#define SAM0_GPIO_PM_BLOCK   SAML21_PM_MODE_BACKUP
 GPIO IRQs require STANDBY mode.
 
#define SAM0_RTCRTT_PM_BLOCK   SAML21_PM_MODE_BACKUP
 RTC/TRR require STANDBY mode.
 
#define SAM0_SPI_PM_BLOCK   SAML21_PM_MODE_STANDBY
 SPI in DMA mode require IDLE mode.
 
#define SAM0_TIMER_PM_BLOCK   SAML21_PM_MODE_STANDBY
 Timers require IDLE mode.
 
#define SAM0_UART_PM_BLOCK   SAML21_PM_MODE_STANDBY
 UART RX IRQ require IDLE mode.
 
#define SAM0_USB_IDLE_PM_BLOCK   SAML21_PM_MODE_BACKUP
 Idle USB require STANDBY mode.
 
#define SAM0_USB_ACTIVE_PM_BLOCK   SAML21_PM_MODE_STANDBY
 Active USB require IDLE mode.
 
#define ADC_INPUTCTRL_MUXPOS_PA02   ADC_INPUTCTRL_MUXPOS_AIN0
 ADC pin aliases. More...
 
#define ADC_INPUTCTRL_MUXPOS_PA03   ADC_INPUTCTRL_MUXPOS_AIN1
 Alias for AIN1.
 
#define ADC_INPUTCTRL_MUXPOS_PB08   ADC_INPUTCTRL_MUXPOS_AIN2
 Alias for AIN2.
 
#define ADC_INPUTCTRL_MUXPOS_PB09   ADC_INPUTCTRL_MUXPOS_AIN3
 Alias for AIN3.
 
#define ADC_INPUTCTRL_MUXPOS_PA04   ADC_INPUTCTRL_MUXPOS_AIN4
 Alias for AIN4.
 
#define ADC_INPUTCTRL_MUXPOS_PA05   ADC_INPUTCTRL_MUXPOS_AIN5
 Alias for AIN5.
 
#define ADC_INPUTCTRL_MUXPOS_PA06   ADC_INPUTCTRL_MUXPOS_AIN6
 Alias for AIN6.
 
#define ADC_INPUTCTRL_MUXPOS_PA07   ADC_INPUTCTRL_MUXPOS_AIN7
 Alias for AIN7.
 
#define ADC_INPUTCTRL_MUXPOS_PB00   ADC_INPUTCTRL_MUXPOS_AIN8
 Alias for AIN8.
 
#define ADC_INPUTCTRL_MUXPOS_PB01   ADC_INPUTCTRL_MUXPOS_AIN9
 Alias for AIN9.
 
#define ADC_INPUTCTRL_MUXPOS_PB02   ADC_INPUTCTRL_MUXPOS_AIN10
 Alias for AIN10.
 
#define ADC_INPUTCTRL_MUXPOS_PB03   ADC_INPUTCTRL_MUXPOS_AIN11
 Alias for AIN11.
 
#define ADC_INPUTCTRL_MUXPOS_PB04   ADC_INPUTCTRL_MUXPOS_AIN12
 Alias for AIN12.
 
#define ADC_INPUTCTRL_MUXPOS_PB05   ADC_INPUTCTRL_MUXPOS_AIN13
 Alias for AIN13.
 
#define ADC_INPUTCTRL_MUXPOS_PB06   ADC_INPUTCTRL_MUXPOS_AIN14
 Alias for AIN14.
 
#define ADC_INPUTCTRL_MUXPOS_PB07   ADC_INPUTCTRL_MUXPOS_AIN15
 Alias for AIN15.
 
#define ADC_INPUTCTRL_MUXPOS_PA08   ADC_INPUTCTRL_MUXPOS_AIN16
 Alias for AIN16.
 
#define ADC_INPUTCTRL_MUXPOS_PA09   ADC_INPUTCTRL_MUXPOS_AIN17
 Alias for AIN17.
 
#define ADC_INPUTCTRL_MUXPOS_PA10   ADC_INPUTCTRL_MUXPOS_AIN18
 Alias for AIN18.
 
#define ADC_INPUTCTRL_MUXPOS_PA11   ADC_INPUTCTRL_MUXPOS_AIN19
 Alias for AIN19.
 
#define ADC_INPUTCTRL_MUXNEG_PA02   ADC_INPUTCTRL_MUXPOS_AIN0
 Alias for AIN0.
 
#define ADC_INPUTCTRL_MUXNEG_PA03   ADC_INPUTCTRL_MUXPOS_AIN1
 Alias for AIN1.
 
#define ADC_INPUTCTRL_MUXNEG_PB08   ADC_INPUTCTRL_MUXPOS_AIN2
 Alias for AIN2.
 
#define ADC_INPUTCTRL_MUXNEG_PB09   ADC_INPUTCTRL_MUXPOS_AIN3
 Alias for AIN3.
 
#define ADC_INPUTCTRL_MUXNEG_PA04   ADC_INPUTCTRL_MUXPOS_AIN4
 Alias for AIN4.
 
#define ADC_INPUTCTRL_MUXNEG_PA05   ADC_INPUTCTRL_MUXPOS_AIN5
 Alias for AIN5.
 
#define ADC_INPUTCTRL_MUXNEG_PA06   ADC_INPUTCTRL_MUXPOS_AIN6
 Alias for AIN6.
 
#define ADC_INPUTCTRL_MUXNEG_PA07   ADC_INPUTCTRL_MUXPOS_AIN7
 Alias for AIN7.
 

Real time counter configuration

#define RTT_MAX_VALUE   (0xffffffff)
 
#define RTT_CLOCK_FREQUENCY   (32768U) /* in Hz */
 
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 512U) /* in Hz */
 
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY) /* in Hz */
 
#define RTT_MIN_OFFSET   (8U)
 

SAML21 GCLK definitions

enum  { SAM0_GCLK_MAIN = 0 , SAM0_GCLK_TIMER = 1 , SAM0_GCLK_32KHZ = 2 , SAM0_GCLK_48MHZ = 3 }
 

Macro Definition Documentation

◆ ADC_INPUTCTRL_MUXPOS_PA02

#define ADC_INPUTCTRL_MUXPOS_PA02   ADC_INPUTCTRL_MUXPOS_AIN0

ADC pin aliases.

Alias for AIN0

Definition at line 90 of file periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
SAM0_GCLK_MAIN 

Main clock.

SAM0_GCLK_TIMER 

4/8MHz clock for timers

SAM0_GCLK_32KHZ 

32 kHz clock

SAM0_GCLK_48MHZ 

48MHz clock

Definition at line 65 of file periph_cpu.h.

Variable Documentation

◆ sam0_adc_pins

const gpio_t sam0_adc_pins[1][20]
static
Initial value:
= {
{
GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8), GPIO_PIN(PB, 9),
GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6), GPIO_PIN(PA, 7),
GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2), GPIO_PIN(PB, 3),
GPIO_PIN(PB, 4), GPIO_PIN(PB, 5), GPIO_PIN(PB, 6), GPIO_PIN(PB, 7),
GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
}
}
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:42
PB
@ PB
port B
Definition: periph_cpu_common.h:96
PA
@ PA
port A
Definition: periph_cpu_common.h:95

Pins that can be used for ADC input.

Definition at line 76 of file periph_cpu.h.