CPU specific definitions for internal peripheral handling. More...

Detailed Description

CPU specific definitions for internal peripheral handling.

Author: Gerson Fernando Budke nando.nosp@m.jve@.nosp@m.gmail.nosp@m..com

Definition in file periph_cpu.h.

#include <avr/io.h>

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Data Structures
struct	uart_conf_t
	UART device configuration. More...

struct	timer_conf_t
	Timer device configuration. More...

struct	i2c_conf_t
	I2C configuration structure. More...

struct	spi_conf_t
	SPI device configuration. More...

Macros
#define	PWR_RED_REG(reg, dev) ((reg << 8) \| dev)
	Define a CPU specific Power Reduction index macro.

#define	GPIO_UNDEF (0xffff)
	Definition of a fitting UNDEF value.

#define	UART_MAX_NUMOF (7)
	Max number of available UARTs.

#define	UART_TXBUF_SIZE (64)
	Size of the UART TX buffer for non-blocking mode.

#define	TIMER_CH_MAX_NUMOF (4)
	Max number of available timer channels.

#define	PERIPH_TIMER_PROVIDES_SET
	A low-level timer_set() implementation is provided.

Typedefs
typedef uint16_t	pwr_reduction_t
	Power Reduction Peripheral Mask.

Enumerations
enum	{ PORT_A , PORT_B , PORT_C , PORT_D , PORT_E , PORT_F , PORT_G , PORT_H , PORT_J , PORT_K , PORT_L , PORT_M , PORT_N , PORT_P , PORT_Q , PORT_R , PORT_MAX }
	Available ports on the ATxmega family. More...

enum	{ PWR_GENERAL_POWER , PWR_PORT_A , PWR_PORT_B , PWR_PORT_C , PWR_PORT_D , PWR_PORT_E , PWR_PORT_F }
	Define a CPU specific Power Reduction index macro.

enum	timer_type_t { TC_TYPE_0 = 0 , TC_TYPE_1 = 1 , TC_TYPE_2 = 2 , TC_TYPE_4 = 4 , TC_TYPE_5 = 5 }
	Timer Type. More...

Length of the CPU_ID in octets
#define	CPUID_LEN (11U)

Power management configuration
#define	PM_NUM_MODES (5)

#define	AVR8_PM_SLEEP_MODE_0 SLEEP_MODE_PWR_DOWN
	Power Down.

#define	AVR8_PM_SLEEP_MODE_1 SLEEP_MODE_PWR_SAVE
	Power Save.

#define	AVR8_PM_SLEEP_MODE_2 SLEEP_MODE_STANDBY
	Standby.

#define	AVR8_PM_SLEEP_MODE_3 SLEEP_MODE_EXT_STANDBY
	Extended Standby.

#define	GPIO_EXT_INT_NUMOF (2 * PORT_MAX)
	Define the number of GPIO interrupts vectors for ATxmega CPU.

#define	HAVE_GPIO_T
	Override GPIO type.

typedef uint16_t	gpio_t

#define	ATXMEGA_GPIO_PIN(x, y) (((x & 0x0f) << 8) \| (y & 0xff))
	Define a CPU specific GPIO pin generator macro. More...

#define	GPIO_PIN(x, y) ATXMEGA_GPIO_PIN(x, (1U << (y & 0x07)))

#define	HAVE_GPIO_MODE_T
	Available pin modes. More...

enum	GPIO_MODE { GPIO_SLEW_RATE = (1 << 7) , GPIO_INVERTED = (1 << 6) , GPIO_OPC_TOTEN = (0 << 3) , GPIO_OPC_BSKPR = (1 << 3) , GPIO_OPC_PD = (2 << 3) , GPIO_OPC_PU = (3 << 3) , GPIO_OPC_WRD_OR = (4 << 3) , GPIO_OPC_WRD_AND = (5 << 3) , GPIO_OPC_WRD_OR_PULL = (6 << 3) , GPIO_OPC_WRD_AND_PULL = (7 << 3) , GPIO_ANALOG = (1 << 1) , GPIO_IN = (0 << 0) , GPIO_OUT = (1 << 0) , GPIO_IN_PU = GPIO_IN \| GPIO_OPC_PU , GPIO_IN_PD = GPIO_IN \| GPIO_OPC_PD , GPIO_OD = GPIO_OUT \| GPIO_OPC_WRD_OR , GPIO_OD_PU = GPIO_OUT \| GPIO_OPC_WRD_OR_PULL }

typedef enum GPIO_MODE	gpio_mode_t

#define	HAVE_GPIO_FLANK_T
	Definition of possible active flanks for external interrupt mode.

enum	gpio_flank_t { GPIO_ISC_BOTH = (0 << 4) , GPIO_ISC_RISING = (1 << 4) , GPIO_ISC_FALLING = (2 << 4) , GPIO_ISC_LOW_LEVEL = (3 << 4) , GPIO_INT_DISABLED_ALL = (1 << 3) , GPIO_INT0_VCT = (0 << 2) , GPIO_INT1_VCT = (1 << 2) , GPIO_LVL_OFF = (0 << 0) , GPIO_LVL_LOW = (1 << 0) , GPIO_LVL_MID = (2 << 0) , GPIO_LVL_HIGH = (3 << 0) , GPIO_FALLING = GPIO_ISC_FALLING \| GPIO_LVL_LOW , GPIO_RISING = GPIO_ISC_RISING \| GPIO_LVL_LOW , GPIO_BOTH = GPIO_ISC_BOTH \| GPIO_LVL_LOW , GPIO_FALLING = 0xff , GPIO_RISING = 0x00 , GPIO_BOTH = 0xab , GPIO_FALLING = GPIOEVENT_EVENT_FALLING_EDGE , GPIO_RISING = GPIOEVENT_EVENT_RISING_EDGE , GPIO_BOTH = GPIO_FALLING \| GPIO_RISING , GPIO_LEVEL_LOW = 0x1 , GPIO_LEVEL_HIGH = 0x2 , GPIO_FALLING = 0x4 , GPIO_RISING = 0x8 , GPIO_BOTH = 0xc , GPIO_FALLING = 0 , GPIO_RISING = 1 , GPIO_BOTH = 2 }

Override I2C clock speed values
#define	HAVE_I2C_SPEED_T

enum	i2c_speed_t { I2C_SPEED_LOW = 10000ul , I2C_SPEED_NORMAL = 100000ul , I2C_SPEED_FAST = 400000ul , I2C_SPEED_FAST_PLUS = 1000000ul , I2C_SPEED_HIGH = 3400000ul , I2C_SPEED_LOW = 10000u , I2C_SPEED_NORMAL = 100000u , I2C_SPEED_FAST = 400000u , I2C_SPEED_FAST_PLUS = 400000u , I2C_SPEED_HIGH = 400000u , I2C_SPEED_LOW = 0 , I2C_SPEED_NORMAL , I2C_SPEED_FAST , I2C_SPEED_FAST_PLUS , I2C_SPEED_HIGH }

#define	PERIPH_SPI_NEEDS_INIT_CS
	Enable common SPI functions.

#define	PERIPH_SPI_NEEDS_TRANSFER_BYTE

#define	PERIPH_SPI_NEEDS_TRANSFER_REG

#define	PERIPH_SPI_NEEDS_TRANSFER_REGS

#define	SPI_UNDEF (UCHAR_MAX)
	Define global value for undefined SPI device.

#define	HAVE_SPI_T
	Define spi_t data type to save data.

typedef uint8_t	spi_t

#define	HAVE_SPI_CLK_T
	Available SPI clock speeds.

enum	spi_clk_t { SPI_CLK_100KHZ = 100000U , SPI_CLK_400KHZ = 400000U , SPI_CLK_1MHZ = 1000000U , SPI_CLK_5MHZ = 5000000U , SPI_CLK_10MHZ = 10000000U , SPI_CLK_100KHZ = KHZ(100) , SPI_CLK_400KHZ = KHZ(400) , SPI_CLK_1MHZ = MHZ(1) , SPI_CLK_5MHZ = MHZ(5) , SPI_CLK_10MHZ = MHZ(10) , SPI_CLK_100KHZ = 100000 , SPI_CLK_400KHZ = 400000 , SPI_CLK_1MHZ = 1000000 , SPI_CLK_5MHZ = 5000000 , SPI_CLK_10MHZ = SPI_CLK_5MHZ , SPI_CLK_100KHZ = KHZ(100) , SPI_CLK_400KHZ = KHZ(400) , SPI_CLK_1MHZ = MHZ(1) , SPI_CLK_5MHZ = MHZ(5) , SPI_CLK_10MHZ = SPI_CLK_5MHZ , SPI_CLK_100KHZ = 0 , SPI_CLK_400KHZ , SPI_CLK_1MHZ , SPI_CLK_5MHZ , SPI_CLK_10MHZ }

Interrupt level used to control nested interrupts
enum	cpu_int_lvl_t { CPU_INT_LVL_OFF , CPU_INT_LVL_LOW , CPU_INT_LVL_MID , CPU_INT_LVL_HIGH }

Macro Definition Documentation

◆ ATXMEGA_GPIO_PIN

#define ATXMEGA_GPIO_PIN	(	x,
		y
	)	(((x & 0x0f) << 8) \| (y & 0xff))

Define a CPU specific GPIO pin generator macro.

The ATxmega internally uses pin mask to manipulate all gpio functions. This allows simultaneous pin actions at any method call. ATxmega specific applications can use ATXMEGA_GPIO_PIN macro to define pins and generic RIOT-OS application should continue to use GPIO_PIN API for compatibility.

Definition at line 135 of file periph_cpu.h.

◆ HAVE_GPIO_MODE_T

#define HAVE_GPIO_MODE_T

Available pin modes.

Generally, a pin can be configured to be input or output. In output mode, a pin can further be put into push-pull or open drain configuration. Though this is supported by most platforms, this is not always the case, so driver implementations may return an error code if a mode is not supported.

Definition at line 148 of file periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Available ports on the ATxmega family.

Enumerator
PORT_A	port A - 600 - 0
PORT_B	port B - 620 - 1
PORT_C	port C - 640 - 2
PORT_D	port D - 660 - 3
PORT_E	port E - 680 - 4
PORT_F	port F - 6A0 - 5
PORT_G	port G - 6C0 - 6
PORT_H	port H - 6E0 - 7
PORT_J	port J - 700 - 8
PORT_K	port K - 720 - 9
PORT_L	port L - 740 - A
PORT_M	port M - 760 - B
PORT_N	port N - 780 - C
PORT_P	port P - 7A0 - D
PORT_Q	port Q - 7C0 - E
PORT_R	port R - 7E0 - F

Definition at line 50 of file periph_cpu.h.

◆ cpu_int_lvl_t

enum cpu_int_lvl_t

Enumerator
CPU_INT_LVL_OFF	Interrupt Disabled
CPU_INT_LVL_LOW	Interrupt Low Level
CPU_INT_LVL_MID	Interrupt Medium Level.
CPU_INT_LVL_HIGH	Interrupt High Level

Definition at line 39 of file periph_cpu.h.

◆ gpio_flank_t

enum gpio_flank_t

Enumerator
GPIO_ISC_BOTH	emit interrupt on both flanks (default)
GPIO_ISC_RISING	emit interrupt on rising flank
GPIO_ISC_FALLING	emit interrupt on falling flank
GPIO_ISC_LOW_LEVEL	emit interrupt on low level
GPIO_INT_DISABLED_ALL	disable all interrupts
GPIO_INT0_VCT	enable interrupt on Vector 0 (default)
GPIO_INT1_VCT	enable interrupt on Vector 1
GPIO_LVL_OFF	interrupt disabled (default)
GPIO_LVL_LOW	interrupt low level
GPIO_LVL_MID	interrupt medium level
GPIO_LVL_HIGH	interrupt higher
GPIO_FALLING	emit interrupt on falling flank
GPIO_RISING	emit interrupt on rising flank
GPIO_BOTH	not supported -> random value
GPIO_FALLING	emit interrupt on falling flank
GPIO_RISING	emit interrupt on rising flank
GPIO_BOTH	emit interrupt on both flanks
GPIO_LEVEL_LOW	emit interrupt level-triggered on low input
GPIO_LEVEL_HIGH	emit interrupt level-triggered on low input
GPIO_FALLING	emit interrupt on falling flank
GPIO_RISING	emit interrupt on rising flank
GPIO_BOTH	emit interrupt on both flanks
GPIO_FALLING	emit interrupt on falling flank
GPIO_RISING	emit interrupt on rising flank
GPIO_BOTH	emit interrupt on both flanks

Definition at line 180 of file periph_cpu.h.

◆ GPIO_MODE

enum GPIO_MODE

Enumerator
GPIO_SLEW_RATE	enable slew rate
GPIO_INVERTED	enable inverted signal
GPIO_OPC_TOTEN	select no pull resistor (TOTEM)
GPIO_OPC_BSKPR	push-pull mode (BUSKEEPER)
GPIO_OPC_PD	pull-down resistor
GPIO_OPC_PU	pull-up resistor
GPIO_OPC_WRD_OR	enable wired OR
GPIO_OPC_WRD_AND	enable wired AND
GPIO_OPC_WRD_OR_PULL	enable wired OR and pull-down resistor
GPIO_OPC_WRD_AND_PULL	enable wired AND and pull-up resistor
GPIO_ANALOG	select GPIO for analog function
GPIO_IN	select GPIO MASK as input
GPIO_OUT	select GPIO MASK as output

Definition at line 149 of file periph_cpu.h.

◆ i2c_speed_t

enum i2c_speed_t

Enumerator
I2C_SPEED_LOW	low speed mode: ~10 kbit/s
I2C_SPEED_NORMAL	normal mode: ~100 kbit/s
I2C_SPEED_FAST	fast mode: ~400 kbit/s
I2C_SPEED_FAST_PLUS	fast plus mode: ~1000 kbit/s
I2C_SPEED_HIGH	high speed mode: ~3400 kbit/s
I2C_SPEED_LOW	low speed mode: ~10 kbit/s
I2C_SPEED_NORMAL	normal mode: ~100 kbit/s
I2C_SPEED_FAST	fast mode: ~400 kbit/s
I2C_SPEED_FAST_PLUS	not supported, capped at 400 kbit/s
I2C_SPEED_HIGH	not supported, capped at 400 kbit/s
I2C_SPEED_LOW	low speed mode: ~10 kbit/s
I2C_SPEED_NORMAL	normal mode: ~100 kbit/s
I2C_SPEED_FAST	fast mode: ~400 kbit/s
I2C_SPEED_FAST_PLUS	fast plus mode: ~1000 kbit/s
I2C_SPEED_HIGH	high speed mode: ~3400 kbit/s

Definition at line 276 of file periph_cpu.h.

◆ spi_clk_t

enum spi_clk_t

Enumerator
SPI_CLK_100KHZ	drive the SPI bus with 100KHz
SPI_CLK_400KHZ	drive the SPI bus with 400KHz
SPI_CLK_1MHZ	drive the SPI bus with 1MHz
SPI_CLK_5MHZ	drive the SPI bus with 5MHz
SPI_CLK_10MHZ	drive the SPI bus with 10MHz
SPI_CLK_100KHZ	drive the SPI bus with 100KHz
SPI_CLK_400KHZ	drive the SPI bus with 400KHz
SPI_CLK_1MHZ	drive the SPI bus with 1MHz
SPI_CLK_5MHZ	drive the SPI bus with 5MHz
SPI_CLK_10MHZ	drive the SPI bus with 10MHz
SPI_CLK_100KHZ	100 kHz
SPI_CLK_400KHZ	400 kHz
SPI_CLK_1MHZ	1 MHz
SPI_CLK_5MHZ	5 MHz
SPI_CLK_10MHZ	10 MHz not supported, falling back to 5 MHz
SPI_CLK_100KHZ	100 kHz
SPI_CLK_400KHZ	400 kHz
SPI_CLK_1MHZ	1 MHz
SPI_CLK_5MHZ	5 MHz
SPI_CLK_10MHZ	10 MHz not supported, falling back to 5 MHz
SPI_CLK_100KHZ	drive the SPI bus with 100KHz
SPI_CLK_400KHZ	drive the SPI bus with 400KHz
SPI_CLK_1MHZ	drive the SPI bus with 1MHz
SPI_CLK_5MHZ	drive the SPI bus with 5MHz
SPI_CLK_10MHZ	drive the SPI bus with 10MHz

Definition at line 352 of file periph_cpu.h.

◆ timer_type_t

enum timer_type_t

Timer Type.

Timer Type 1 is equal to Type 0 (two channels instead four) Timer Type 2 is Type 0 configured as two 8 bit timers instead one 16 bit Timer Type 2 won't be available as a standard timer Timer Type 5 is equal to Type 4 (two channels instead four)

Definition at line 250 of file periph_cpu.h.

Detailed Description

Data Structures

Macros

Typedefs

Enumerations

Length of the CPU_ID in octets

Power management configuration

Override I2C clock speed values

Interrupt level used to control nested interrupts