periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* Add specific clock configuration (HSE, LSE) for this board here */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 #include "periph_cpu.h"
28 #include "clk_conf.h"
29 #include "cfg_i2c1_pb8_pb9.h"
30 #include "cfg_rtt_default.h"
31 #include "cfg_usb_otg_fs.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
41 static const timer_conf_t timer_config[] = {
42  {
43  .dev = TIM2,
44  .max = 0xffffffff,
45  .rcc_mask = RCC_APB1ENR1_TIM2EN,
46  .bus = APB1,
47  .irqn = TIM2_IRQn
48  },
49  {
50  .dev = TIM5,
51  .max = 0xffffffff,
52  .rcc_mask = RCC_APB1ENR1_TIM5EN,
53  .bus = APB1,
54  .irqn = TIM5_IRQn
55  },
56 };
57 
58 #define TIMER_0_ISR isr_tim2
59 #define TIMER_1_ISR isr_tim5
60 
61 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
68 static const uart_conf_t uart_config[] = {
69  {
70  .dev = LPUART1,
71  .rcc_mask = RCC_APB1ENR2_LPUART1EN,
72  .rx_pin = GPIO_PIN(PORT_G, 8),
73  .tx_pin = GPIO_PIN(PORT_G, 7),
74  .rx_af = GPIO_AF8,
75  .tx_af = GPIO_AF8,
76  .bus = APB12,
77  .irqn = LPUART1_IRQn,
78  .type = STM32_LPUART,
79  .clk_src = 0,
80  },
81  {
82  .dev = USART3,
83  .rcc_mask = RCC_APB1ENR1_USART3EN,
84  .rx_pin = GPIO_PIN(PORT_D, 9),
85  .tx_pin = GPIO_PIN(PORT_D, 8),
86  .rx_af = GPIO_AF7,
87  .tx_af = GPIO_AF7,
88  .bus = APB1,
89  .irqn = USART3_IRQn,
90  .type = STM32_USART,
91  .clk_src = 0, /* Use APB clock */
92 #ifdef UART_USE_DMA
93  .dma_stream = 5,
94  .dma_chan = 4
95 #endif
96  }
97 };
98 
99 #define UART_0_ISR (isr_lpuart1)
100 #define UART_1_ISR (isr_usart3)
101 #define UART_1_DMA_ISR (isr_dma1_stream5)
102 
103 #define UART_NUMOF ARRAY_SIZE(uart_config)
110 static const pwm_conf_t pwm_config[] = {
111  {
112  .dev = TIM1,
113  .rcc_mask = RCC_APB2ENR_TIM1EN,
114  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
115  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
116  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
117  { .pin = GPIO_UNDEF, .cc_chan = 0} },
118  .af = GPIO_AF1,
119  .bus = APB2
120  },
121  {
122  .dev = TIM4,
123  .rcc_mask = RCC_APB1ENR1_TIM4EN,
124  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
125  { .pin = GPIO_UNDEF, .cc_chan = 0},
126  { .pin = GPIO_UNDEF, .cc_chan = 0},
127  { .pin = GPIO_UNDEF, .cc_chan = 0} },
128  .af = GPIO_AF2,
129  .bus = APB1
130  },
131 };
132 
133 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
140 static const spi_conf_t spi_config[] = {
141  {
142  .dev = SPI1,
143  .mosi_pin = GPIO_PIN(PORT_A, 7),
144  .miso_pin = GPIO_PIN(PORT_A, 6),
145  .sclk_pin = GPIO_PIN(PORT_A, 5),
146  .cs_pin = SPI_CS_UNDEF,
147  .mosi_af = GPIO_AF5,
148  .miso_af = GPIO_AF5,
149  .sclk_af = GPIO_AF5,
150  .cs_af = GPIO_AF5,
151  .rccmask = RCC_APB2ENR_SPI1EN,
152  .apbbus = APB2
153  }
154 };
155 
156 #define SPI_NUMOF ARRAY_SIZE(spi_config)
187 static const adc_conf_t adc_config[] = {
188  { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 8 }, /* ADC12_IN8 */
189  { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 1 }, /* ADC123_IN1 */
190  { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 4 }, /* ADC123_IN4 */
191  { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* ADC123_IN2 */
192  { .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 13 }, /* ADC12_IN13 */
193  { .pin = GPIO_PIN(PORT_C, 5), .dev = 0, .chan = 14 }, /* ADC12_IN14 */
194  { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 },
195 };
196 
200 #define ADC_NUMOF ARRAY_SIZE(adc_config)
201 
205 #define VBAT_ADC ADC_LINE(6)
206 
209 #ifdef __cplusplus
210 }
211 #endif
212 
213 #endif /* PERIPH_CONF_H */
@ PORT_G
port G
Definition: periph_cpu.h:53
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_E
port E
Definition: periph_cpu.h:51
@ PORT_A
port A
Definition: periph_cpu.h:47
@ PORT_D
port D
Definition: periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:40
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:187
Common configuration for STM32 I2C.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:111
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: cpu_uart.h:39
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
ADC device configuration.
Definition: periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:288
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
Timer device configuration.
Definition: periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:265
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219