periph_conf.h
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1 /*
2  * Copyright (C) 2017 Kees Bakker, SODAQ
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include <stdint.h>
23 
24 #include "cpu.h"
25 #include "periph_cpu.h"
26 #include "cfg_clock_default.h"
27 #include "cfg_rtc_default.h"
28 #include "cfg_rtt_default.h"
29 #include "cfg_timer_default.h"
30 #include "cfg_usbdev_default.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
41 static const uart_conf_t uart_config[] = {
42  {
43  .dev = &SERCOM5->USART,
44  .rx_pin = GPIO_PIN(PB,3), /* D0, RX Pin */
45  .tx_pin = GPIO_PIN(PB,2), /* D1, TX Pin */
46 #ifdef MODULE_PERIPH_UART_HW_FC
47  .rts_pin = GPIO_UNDEF,
48  .cts_pin = GPIO_UNDEF,
49 #endif
50  .mux = GPIO_MUX_D,
51  .rx_pad = UART_PAD_RX_1,
52  .tx_pad = UART_PAD_TX_0,
53  .flags = UART_FLAG_NONE,
54  .gclk_src = SAM0_GCLK_MAIN,
55  },
56  {
57  .dev = &SERCOM2->USART,
58  .rx_pin = GPIO_PIN(PA,13),
59  .tx_pin = GPIO_PIN(PA,12),
60 #ifdef MODULE_PERIPH_UART_HW_FC
61  .rts_pin = GPIO_UNDEF,
62  .cts_pin = GPIO_UNDEF,
63 #endif
64  .mux = GPIO_MUX_C,
65  .rx_pad = UART_PAD_RX_1,
66  .tx_pad = UART_PAD_TX_0,
67  .flags = UART_FLAG_NONE,
68  .gclk_src = SAM0_GCLK_MAIN,
69  },
70 };
71 
72 /* interrupt function name mapping */
73 #define UART_0_ISR isr_sercom5
74 #define UART_1_ISR isr_sercom2
75 
76 #define UART_NUMOF ARRAY_SIZE(uart_config)
84 /* ADC Default values */
85 #define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
86 
87 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
88 #define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_DIV2
89 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
90 
91 static const adc_conf_chan_t adc_channels[] = {
92  /* port, pin, muxpos */
93  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA02 }, /* A0 */
94  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA03 }, /* A1 */
95  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB08 }, /* A2 */
96  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB09 }, /* A3 */
97  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA06 }, /* A4 */
98  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA07 }, /* A5 */
99  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA08 }, /* A6 */
100  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA09 }, /* A7 */
101  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA10 }, /* A8 */
102  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA11 }, /* A9 */
103 #if 0
104  /* These pins are also used for RX/TX uart0 */
105  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB02 }, /* A10, TX */
106  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB03 }, /* A11, RX */
107 #endif
108 
109  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA05 }, /* BAT_VOLT */
110 };
111 
112 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
119 static const spi_conf_t spi_config[] = {
120  {
121  .dev = &SERCOM0->SPI,
122  .miso_pin = GPIO_PIN(PA, 8),
123  .mosi_pin = GPIO_PIN(PA, 10),
124  .clk_pin = GPIO_PIN(PA, 11),
125  .miso_mux = GPIO_MUX_C,
126  .mosi_mux = GPIO_MUX_C,
127  .clk_mux = GPIO_MUX_C,
128  .miso_pad = SPI_PAD_MISO_0,
129  .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
130  .gclk_src = SAM0_GCLK_MAIN,
131 #ifdef MODULE_PERIPH_DMA
132  .tx_trigger = SERCOM0_DMAC_ID_TX,
133  .rx_trigger = SERCOM0_DMAC_ID_RX,
134 #endif
135  }
136 };
137 
138 #define SPI_NUMOF ARRAY_SIZE(spi_config)
145 static const i2c_conf_t i2c_config[] = {
146  {
147  .dev = &(SERCOM3->I2CM),
148  .speed = I2C_SPEED_NORMAL,
149  .scl_pin = GPIO_PIN(PA, 23),
150  .sda_pin = GPIO_PIN(PA, 22),
151  .mux = GPIO_MUX_C,
152  .gclk_src = SAM0_GCLK_MAIN,
153  .flags = I2C_FLAG_NONE
154  }
155 };
156 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
159 #ifdef __cplusplus
160 }
161 #endif
162 
163 #endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
Default RTC configuration for SODAQ boards.
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_2_SCK_3
use pad 2 for MOSI, pad 3 for SCK
#define ADC_INPUTCTRL_MUXPOS_PA05
Alias for PIN5.
Definition: periph_cpu.h:124
#define ADC_INPUTCTRL_MUXPOS_PB08
Alias for PIN2.
Definition: periph_cpu.h:121
#define ADC_INPUTCTRL_MUXPOS_PB02
Alias for PIN10.
Definition: periph_cpu.h:129
#define ADC_INPUTCTRL_MUXPOS_PA10
Alias for PIN18.
Definition: periph_cpu.h:137
#define ADC_INPUTCTRL_MUXPOS_PA11
Alias for PIN19.
Definition: periph_cpu.h:138
#define ADC_INPUTCTRL_MUXPOS_PA08
Alias for PIN16.
Definition: periph_cpu.h:135
#define ADC_INPUTCTRL_MUXPOS_PB09
Alias for PIN3.
Definition: periph_cpu.h:122
#define ADC_INPUTCTRL_MUXPOS_PA09
Alias for PIN17.
Definition: periph_cpu.h:136
#define ADC_INPUTCTRL_MUXPOS_PA07
Alias for PIN7.
Definition: periph_cpu.h:126
#define ADC_INPUTCTRL_MUXPOS_PB03
Alias for PIN11.
Definition: periph_cpu.h:130
#define ADC_INPUTCTRL_MUXPOS_PA06
Alias for PIN6.
Definition: periph_cpu.h:125
#define ADC_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition: periph_cpu.h:119
#define ADC_INPUTCTRL_MUXPOS_PA03
Alias for PIN1.
Definition: periph_cpu.h:120
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:74
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219