periph_conf.h File Reference
Configuration of CPU peripherals for STM32F746G-DISCO board. More...
Detailed Description
Configuration of CPU peripherals for STM32F746G-DISCO board.
Definition in file periph_conf.h.
#include <stdint.h>#include "periph_cpu.h"#include "clk_conf.h"#include "cfg_rtt_default.h"#include "cfg_timer_tim2.h"#include "cfg_usb_otg_fs.h"#include "mii.h"
Include dependency graph for periph_conf.h: This graph shows which files directly or indirectly include this file:Go to the source code of this file.
| #define | CONFIG_BOARD_HAS_LSE 1 |
| #define | CONFIG_BOARD_HAS_HSE 1 |
| #define | CONFIG_CLOCK_HSE MHZ(25) |
DMA streams configuration | |
| #define | DMA_0_ISR isr_dma2_stream7 |
| #define | DMA_1_ISR isr_dma2_stream6 |
| #define | DMA_2_ISR isr_dma1_stream6 |
| #define | DMA_3_ISR isr_dma2_stream2 |
| #define | DMA_4_ISR isr_dma2_stream5 |
| #define | DMA_5_ISR isr_dma2_stream3 |
| #define | DMA_6_ISR isr_dma2_stream4 |
| #define | DMA_7_ISR isr_dma2_stream0 |
| #define | DMA_NUMOF ARRAY_SIZE(dma_config) |
| static const dma_conf_t | dma_config [] |
UART configuration | |
| #define | UART_0_ISR (isr_usart1) |
| #define | UART_0_DMA_ISR (isr_dma2_stream7) |
| #define | UART_6_ISR (isr_usart6) |
| #define | UART_6_DMA_ISR (isr_dma2_stream6) |
| #define | UART_NUMOF ARRAY_SIZE(uart_config) |
| static const uart_conf_t | uart_config [] |
SPI configuration | |
| #define | SPI_NUMOF ARRAY_SIZE(spi_config) |
| static const spi_conf_t | spi_config [] |
I2C configuration | |
| #define | I2C_0_ISR isr_i2c1_er |
| #define | I2C_1_ISR isr_i2c3_er |
| #define | I2C_NUMOF ARRAY_SIZE(i2c_config) |
| static const i2c_conf_t | i2c_config [] |
ETH configuration | |
| #define | ETH_DMA_ISR isr_dma2_stream0 |
| static const eth_conf_t | eth_config |
USB OTG FS configuration using ULPI HS PHY | |
The USB OTG HS peripheral uses a ULPI HS PHY. The configuration of the ULPI HS PHY interface is board-specific. | |
| #define | DWC2_USB_OTG_HS_ENABLED |
| Enable the high speed USB OTG peripheral. | |
| #define | USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config) |
| Number of available USB OTG peripherals. | |
| static const dwc2_usb_otg_fshs_config_t | dwc2_usb_otg_fshs_config [] |
| Common USB OTG HS configuration with ULPI HS PHY. More... | |
FMC configuration | |
| #define | FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config) |
| Number of configured FMC banks. | |
| static const fmc_conf_t | fmc_config |
| FMC controller configuration. | |
| static const fmc_bank_conf_t | fmc_bank_config [] |
| FMC Bank configuration. More... | |
SDIO/SDMMC configuration | |
| #define | SDMMC_CONFIG_NUMOF 1 |
| Number of configured SDIO/SDMMC peripherals. | |
| static const sdmmc_conf_t | sdmmc_config [] |
| SDIO/SDMMC static configuration struct. More... | |
LTDC configuration | |
| static const ltdc_conf_t | ltdc_config |
| LTDC static configuration struct. | |
Variable Documentation
◆ dma_config
|
static |
Initial value:
= {
{ .stream = 15 },
{ .stream = 14 },
{ .stream = 6 },
{ .stream = 3 },
{ .stream = 4 },
{ .stream = 11 },
{ .stream = 12 },
{ .stream = 8 },
}
Definition at line 58 of file periph_conf.h.
◆ dwc2_usb_otg_fshs_config
|
static |
Initial value:
= {
{
.periph = USB_OTG_HS_PERIPH_BASE,
.type = DWC2_USB_OTG_HS,
.phy = DWC2_USB_OTG_PHY_ULPI,
.rcc_mask = RCC_AHB1ENR_OTGHSEN,
.irqn = OTG_HS_IRQn,
.ahb = AHB1,
.ulpi_af = GPIO_AF10,
}
}
Common USB OTG HS configuration with ULPI HS PHY.
Definition at line 293 of file periph_conf.h.
◆ eth_config
|
static |
Initial value:
= {
.mode = RMII,
.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
.dma = 7,
.dma_chan = 8,
.phy_addr = 0x00,
.pins = {
}
}
Definition at line 196 of file periph_conf.h.
◆ fmc_bank_config
|
static |
FMC Bank configuration.
The board has a SDRAM IS42S32400F-6BL with 128 MBit on-board. It is organized in 4 banks of 1M x 32 bits each and connected to bank 5 at address 0xc0000000.
- Note
- Since only D0 to D15 are connected and D16 to D31 are unused, 4 banks with only 1M x 16 bits and thus half the capacity (8 MByte) can be used.
Definition at line 394 of file periph_conf.h.
◆ i2c_config
|
static |
Initial value:
= {
{
.dev = I2C1,
.speed = I2C_SPEED_NORMAL,
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C1EN,
.rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
.irqn = I2C1_ER_IRQn,
},
{
.dev = I2C3,
.speed = I2C_SPEED_NORMAL,
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C3EN,
.rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
.irqn = I2C3_ER_IRQn,
},
}
Definition at line 159 of file periph_conf.h.
◆ sdmmc_config
|
static |
Initial value:
= {
{
.dev = SDMMC1,
.bus = APB2,
.rcc_mask = RCC_APB2ENR_SDMMC1EN,
.cd_active = 0,
.cd_mode = GPIO_IN_PU,
.irqn = SDMMC1_IRQn
},
}
SDIO/SDMMC static configuration struct.
Definition at line 442 of file periph_conf.h.
◆ spi_config
|
static |
Initial value:
= {
{
.dev = SPI2,
.sclk_pin = GPIO_PIN(PORT_I, 1),
.cs_pin = SPI_CS_UNDEF,
.mosi_af = GPIO_AF5,
.miso_af = GPIO_AF5,
.sclk_af = GPIO_AF5,
.cs_af = GPIO_AF5,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1,
},
}
Definition at line 130 of file periph_conf.h.
◆ uart_config
|
static |
Initial value:
= {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn,
},
{
.dev = USART6,
.rcc_mask = RCC_APB2ENR_USART6EN,
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART6_IRQn,
},
}
Definition at line 87 of file periph_conf.h.
