cfg_spi_default.h

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/*
 * Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
 *               2023 Gunar Schorcht <gunar@schorcht.net>
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef CFG_SPI_DEFAULT_H
#define CFG_SPI_DEFAULT_H
 
#include "periph_cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifndef SPI_DEV_1_USED
#define SPI_DEV_1_USED  0
#endif
 
#ifndef SPI_DEV_0_CS
#define SPI_DEV_0_CS    GPIO_PIN(PORT_B, 12)
#endif
 
#ifndef SPI_DEV_1_CS
#define SPI_DEV_1_CS    GPIO_PIN(PORT_B, 5)
#endif
 
static const spi_conf_t spi_config[] = {
    {
        .dev      = SPI1,
        .mosi_pin = GPIO_PIN(PORT_B, 15),
        .miso_pin = GPIO_PIN(PORT_B, 14),
        .sclk_pin = GPIO_PIN(PORT_B, 13),
        .cs_pin   = SPI_DEV_0_CS,
        .rcumask  = RCU_APB1EN_SPI1EN_Msk,
        .apbbus   = APB1,
    },
#if SPI_DEV_1_USED
    {
        .dev      = SPI0,
        .mosi_pin = GPIO_PIN(PORT_A, 7),
        .miso_pin = GPIO_PIN(PORT_A, 6),
        .sclk_pin = GPIO_PIN(PORT_A, 5),
        .cs_pin   = SPI_DEV_1_CS,
        .rcumask  = RCU_APB2EN_SPI0EN_Msk,
        .apbbus   = APB2,
    },
#endif
};
 
#define SPI_NUMOF           ARRAY_SIZE(spi_config)
#ifdef __cplusplus
}
#endif
 
#endif /* CFG_SPI_DEFAULT_H */