periph_conf.h

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/*
 * SPDX-FileCopyrightText: 2019 twostairs
 * SPDX-FileCopyrightText: 2017 Inria
 * SPDX-FileCopyrightText: 2017 OTA keys
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE            1
#endif
 
#include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb6_pb7.h"
#include "cfg_timer_tim2.h"
#include "cfg_rtt_default.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
static const uart_conf_t uart_config[] = {
    {
        .dev        = USART2,
        .rcc_mask   = RCC_APB1ENR1_USART2EN,
        .rx_pin     = GPIO_PIN(PORT_A, 15),
        .tx_pin     = GPIO_PIN(PORT_A, 2),
        .rx_af      = GPIO_AF3,
        .tx_af      = GPIO_AF7,
        .bus        = APB1,
        .irqn       = USART2_IRQn,
        .type       = STM32_USART,
        .clk_src    = 0, /* Use APB clock */
    },
    {
        .dev        = USART1,
        .rcc_mask   = RCC_APB2ENR_USART1EN,
        .rx_pin     = GPIO_PIN(PORT_A, 10),
        .tx_pin     = GPIO_PIN(PORT_A, 9),
        .rx_af      = GPIO_AF7,
        .tx_af      = GPIO_AF7,
        .bus        = APB2,
        .irqn       = USART1_IRQn,
        .type       = STM32_USART,
        .clk_src    = 0, /* Use APB clock */
    },
};
 
#define UART_0_ISR          (isr_usart2)
#define UART_1_ISR          (isr_usart1)
 
#define UART_NUMOF          ARRAY_SIZE(uart_config)
static const pwm_conf_t pwm_config[] = {
    {
        .dev      = TIM1,
        .rcc_mask = RCC_APB2ENR_TIM1EN,
        .chan     = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
                      { .pin = GPIO_UNDEF,                   .cc_chan = 0 },
                      { .pin = GPIO_UNDEF,                   .cc_chan = 0 },
                      { .pin = GPIO_UNDEF,                   .cc_chan = 0 } },
        .af       = GPIO_AF1,
        .bus      = APB2
    }
};
 
#define PWM_NUMOF           ARRAY_SIZE(pwm_config)
static const spi_conf_t spi_config[] = {
    {
        .dev      = SPI1,
        .mosi_pin = GPIO_PIN(PORT_B, 5),
        .miso_pin = GPIO_PIN(PORT_B, 4),
        .sclk_pin = GPIO_PIN(PORT_B, 3),
        .cs_pin   = SPI_CS_UNDEF,
        .mosi_af  = GPIO_AF5,
        .miso_af  = GPIO_AF5,
        .sclk_af  = GPIO_AF5,
        .cs_af    = GPIO_AF5,
        .rccmask  = RCC_APB2ENR_SPI1EN,
        .apbbus   = APB2
    }
};
 
#define SPI_NUMOF           ARRAY_SIZE(spi_config)
static const adc_conf_t adc_config[] = {
    {GPIO_PIN(PORT_A, 0),  .dev = 0, .chan = 5},  /* ADC1_IN5  */
    {GPIO_PIN(PORT_A, 1),  .dev = 0, .chan = 6},  /* ADC1_IN6  */
    {GPIO_PIN(PORT_A, 3),  .dev = 0, .chan = 8},  /* ADC1_IN8  */
    {GPIO_PIN(PORT_A, 4),  .dev = 0, .chan = 9},  /* ADC1_IN9  */
    {GPIO_PIN(PORT_A, 7),  .dev = 0, .chan = 12}, /* ADC1_IN12 */
    {GPIO_UNDEF,           .dev = 0, .chan = 18}, /* VBAT */
};
 
#define ADC_NUMOF           ARRAY_SIZE(adc_config)
 
#define VBAT_ADC            ADC_LINE(5) 
#ifdef __cplusplus
}
#endif