periph_conf.h
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1 /*
2  * Copyright (C) 2021 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 /* This board provides an LSE */
22 #ifndef CONFIG_BOARD_HAS_LSE
23 #define CONFIG_BOARD_HAS_LSE 1
24 #endif
25 
26 /* This board provides an HSE */
27 #ifndef CONFIG_BOARD_HAS_HSE
28 #define CONFIG_BOARD_HAS_HSE 1
29 #endif
30 
31 /* The HSE provides a 25MHz clock */
32 #ifndef CONFIG_CLOCK_HSE
33 #define CONFIG_CLOCK_HSE MHZ(25)
34 #endif
35 
36 #include <stdint.h>
37 
38 #include "periph_cpu.h"
39 #include "clk_conf.h"
40 #include "cfg_rtt_default.h"
41 #include "cfg_timer_tim2.h"
42 #if defined(MODULE_PERIPH_USBDEV_HS_ULPI)
43 #include "usbdev_synopsys_dwc2.h"
44 #else
45 #include "cfg_usb_otg_fs.h"
46 #endif
47 #include "mii.h"
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
57 static const dma_conf_t dma_config[] = {
58  { .stream = 15 }, /* DMA2 Stream 7 - USART1_TX */
59  { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
60  { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
61  { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
62  { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
63  { .stream = 11 }, /* DMA2 Stream 3 - SPI4_RX Ch5 / SDMMC1 Ch 4 */
64  { .stream = 12 }, /* DMA2 Stream 4 - SPI4_TX */
65  { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
66 };
67 
68 #define DMA_0_ISR isr_dma2_stream7
69 #define DMA_1_ISR isr_dma2_stream6
70 #define DMA_2_ISR isr_dma1_stream6
71 
72 #define DMA_3_ISR isr_dma2_stream2
73 #define DMA_4_ISR isr_dma2_stream5
74 #define DMA_5_ISR isr_dma2_stream3
75 #define DMA_6_ISR isr_dma2_stream4
76 
77 #define DMA_7_ISR isr_dma2_stream0
78 
79 #define DMA_NUMOF ARRAY_SIZE(dma_config)
86 static const uart_conf_t uart_config[] = {
87  {
88  .dev = USART1,
89  .rcc_mask = RCC_APB2ENR_USART1EN,
90  .rx_pin = GPIO_PIN(PORT_B, 7),
91  .tx_pin = GPIO_PIN(PORT_A, 9),
92  .rx_af = GPIO_AF7,
93  .tx_af = GPIO_AF7,
94  .bus = APB2,
95  .irqn = USART1_IRQn,
96 #ifdef MODULE_PERIPH_DMA
97  .dma = 0,
98  .dma_chan = 4
99 #endif
100  },
101  { /* Arduino connectors */
102  .dev = USART6,
103  .rcc_mask = RCC_APB2ENR_USART6EN,
104  .rx_pin = GPIO_PIN(PORT_C, 6),
105  .tx_pin = GPIO_PIN(PORT_C, 7),
106  .rx_af = GPIO_AF7,
107  .tx_af = GPIO_AF7,
108  .bus = APB2,
109  .irqn = USART6_IRQn,
110 #ifdef MODULE_PERIPH_DMA
111  .dma = 1,
112  .dma_chan = 5
113 #endif
114  },
115 };
116 
117 #define UART_0_ISR (isr_usart1)
118 #define UART_0_DMA_ISR (isr_dma2_stream7)
119 #define UART_6_ISR (isr_usart6)
120 #define UART_6_DMA_ISR (isr_dma2_stream6)
121 
122 #define UART_NUMOF ARRAY_SIZE(uart_config)
129 static const spi_conf_t spi_config[] = {
130  {
131  .dev = SPI2,
132  .mosi_pin = GPIO_PIN(PORT_B, 15),
133  .miso_pin = GPIO_PIN(PORT_B, 14),
134  .sclk_pin = GPIO_PIN(PORT_I, 1),
135  .cs_pin = SPI_CS_UNDEF,
136  .mosi_af = GPIO_AF5,
137  .miso_af = GPIO_AF5,
138  .sclk_af = GPIO_AF5,
139  .cs_af = GPIO_AF5,
140  .rccmask = RCC_APB1ENR_SPI2EN,
141  .apbbus = APB1,
142 #ifdef MODULE_PERIPH_DMA
143  .tx_dma = 4,
144  .tx_dma_chan = 0,
145  .rx_dma = 3,
146  .rx_dma_chan = 0,
147 #endif
148  },
149 };
150 
151 #define SPI_NUMOF ARRAY_SIZE(spi_config)
158 static const i2c_conf_t i2c_config[] = {
159  {
160  .dev = I2C1,
161  .speed = I2C_SPEED_NORMAL,
162  .scl_pin = GPIO_PIN(PORT_B, 8),
163  .sda_pin = GPIO_PIN(PORT_B, 9),
164  .scl_af = GPIO_AF4,
165  .sda_af = GPIO_AF4,
166  .bus = APB1,
167  .rcc_mask = RCC_APB1ENR_I2C1EN,
168  .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
169  .irqn = I2C1_ER_IRQn,
170  },
171  {
172  .dev = I2C3,
173  .speed = I2C_SPEED_NORMAL,
174  .scl_pin = GPIO_PIN(PORT_H, 7),
175  .sda_pin = GPIO_PIN(PORT_H, 8),
176  .scl_af = GPIO_AF4,
177  .sda_af = GPIO_AF4,
178  .bus = APB1,
179  .rcc_mask = RCC_APB1ENR_I2C3EN,
180  .rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
181  .irqn = I2C3_ER_IRQn,
182  },
183 };
184 
185 #define I2C_0_ISR isr_i2c1_er
186 #define I2C_1_ISR isr_i2c3_er
187 
188 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
195 static const eth_conf_t eth_config = {
196  .mode = RMII,
198  .dma = 7,
199  .dma_chan = 8,
200  .phy_addr = 0x00,
201  .pins = {
202  GPIO_PIN(PORT_G, 13), /* TXD0 */
203  GPIO_PIN(PORT_G, 14), /* TXD1 */
204  GPIO_PIN(PORT_G, 11), /* TX_EN */
205  GPIO_PIN(PORT_C, 4), /* RXD0 */
206  GPIO_PIN(PORT_C, 5), /* RXD1 */
207  GPIO_PIN(PORT_A, 7), /* CRS_DV */
208  GPIO_PIN(PORT_C, 1), /* MDC */
209  GPIO_PIN(PORT_A, 2), /* MDIO */
210  GPIO_PIN(PORT_A, 1), /* REF_CLK */
211  }
212 };
213 
214 #define ETH_DMA_ISR isr_dma2_stream0
222 static const ltdc_conf_t ltdc_config = {
223  .bus = APB2,
224  .rcc_mask = RCC_APB2ENR_LTDCEN,
225  .clk_pin = { .pin = GPIO_PIN(PORT_I, 14), .af = GPIO_AF14, },
226  .de_pin = { .pin = GPIO_PIN(PORT_K, 7), .af = GPIO_AF14, },
227  .hsync_pin = { .pin = GPIO_PIN(PORT_I, 10), .af = GPIO_AF14, },
228  .vsync_pin = { .pin = GPIO_PIN(PORT_I, 9), .af = GPIO_AF14, },
229  .r_pin = {
230  { .pin = GPIO_PIN(PORT_I, 15), .af = GPIO_AF14, },
231  { .pin = GPIO_PIN(PORT_J, 0), .af = GPIO_AF14, },
232  { .pin = GPIO_PIN(PORT_J, 1), .af = GPIO_AF14, },
233  { .pin = GPIO_PIN(PORT_J, 2), .af = GPIO_AF14, },
234  { .pin = GPIO_PIN(PORT_J, 3), .af = GPIO_AF14, },
235  { .pin = GPIO_PIN(PORT_J, 4), .af = GPIO_AF14, },
236  { .pin = GPIO_PIN(PORT_J, 5), .af = GPIO_AF14, },
237  { .pin = GPIO_PIN(PORT_J, 6), .af = GPIO_AF14, },
238  },
239  .g_pin = {
240  { .pin = GPIO_PIN(PORT_J, 7), .af = GPIO_AF14, },
241  { .pin = GPIO_PIN(PORT_J, 8), .af = GPIO_AF14, },
242  { .pin = GPIO_PIN(PORT_J, 9), .af = GPIO_AF14, },
243  { .pin = GPIO_PIN(PORT_J, 10), .af = GPIO_AF14, },
244  { .pin = GPIO_PIN(PORT_J, 11), .af = GPIO_AF14, },
245  { .pin = GPIO_PIN(PORT_K, 0), .af = GPIO_AF14, },
246  { .pin = GPIO_PIN(PORT_K, 1), .af = GPIO_AF14, },
247  { .pin = GPIO_PIN(PORT_K, 2), .af = GPIO_AF14, },
248  },
249  .b_pin = {
250  { .pin = GPIO_PIN(PORT_E, 4), .af = GPIO_AF14, },
251  { .pin = GPIO_PIN(PORT_J, 13), .af = GPIO_AF14, },
252  { .pin = GPIO_PIN(PORT_J, 14), .af = GPIO_AF14, },
253  { .pin = GPIO_PIN(PORT_J, 15), .af = GPIO_AF14, },
254  { .pin = GPIO_PIN(PORT_G, 12), .af = GPIO_AF9, },
255  { .pin = GPIO_PIN(PORT_K, 4), .af = GPIO_AF14, },
256  { .pin = GPIO_PIN(PORT_K, 5), .af = GPIO_AF14, },
257  { .pin = GPIO_PIN(PORT_K, 6), .af = GPIO_AF14, },
258  },
259  /* values below come from STM32CubeF7 code and differ from the typical
260  * values mentioned in the RK043FN48H datasheet. Both sets of values work
261  * with the display.
262  * See the discussion in
263  * https://community.st.com/s/question/0D50X0000BOvdWP/how-to-set-displays-parameters-
264  */
265  .hsync = 41,
266  .vsync = 10,
267  .hbp = 13,
268  .hfp = 32,
269  .vbp = 2,
270  .vfp = 2,
271 };
274 #if defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN
287 #define DWC2_USB_OTG_HS_ENABLED
288 
293  {
294  .periph = USB_OTG_HS_PERIPH_BASE,
295  .type = DWC2_USB_OTG_HS,
296  .phy = DWC2_USB_OTG_PHY_ULPI,
297  .rcc_mask = RCC_AHB1ENR_OTGHSEN,
298  .irqn = OTG_HS_IRQn,
299  .ahb = AHB1,
300  .ulpi_af = GPIO_AF10,
301  .ulpi_clk = GPIO_PIN(PORT_A, 5),
302  .ulpi_d0 = GPIO_PIN(PORT_A, 3),
303  .ulpi_d1 = GPIO_PIN(PORT_B, 0),
304  .ulpi_d2 = GPIO_PIN(PORT_B, 1),
305  .ulpi_d3 = GPIO_PIN(PORT_B, 10),
306  .ulpi_d4 = GPIO_PIN(PORT_B, 11),
307  .ulpi_d5 = GPIO_PIN(PORT_B, 12),
308  .ulpi_d6 = GPIO_PIN(PORT_B, 13),
309  .ulpi_d7 = GPIO_PIN(PORT_B, 5),
310  .ulpi_dir = GPIO_PIN(PORT_C, 2),
311  .ulpi_stp = GPIO_PIN(PORT_C, 0),
312  .ulpi_nxt = GPIO_PIN(PORT_H, 4),
313  }
314 };
315 
319 #define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
320 
322 #endif /* defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN */
323 
331 static const fmc_conf_t fmc_config = {
332  .bus = AHB3,
333  .rcc_mask = RCC_AHB3ENR_FMCEN,
334 #if MODULE_PERIPH_FMC_SDRAM
335  .ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* FMC_BA0 signal */
336  .ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* FMC_BA1 signal */
337  .sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, }, /* FMC_SDCLK signal */
338  .sdnwe_pin = { .pin = GPIO_PIN(PORT_H, 5), .af = GPIO_AF12, }, /* FMC_SDNWE signal */
339  .sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* FMC_SDNRAS signal */
340  .sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* FMC_SDNCAS signal */
341  .sdcke0_pin = { .pin = GPIO_PIN(PORT_C, 3), .af = GPIO_AF12, }, /* FMC_SDCKE0 signal */
342  .sdne0_pin = { .pin = GPIO_PIN(PORT_H, 3), .af = GPIO_AF12, }, /* FMC_SDNE0 signal */
343  .addr = {
344  { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* FMC_A0 signal */
345  { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* FMC_A1 signal */
346  { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* FMC_A2 signal */
347  { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* FMC_A3 signal */
348  { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* FMC_A4 signal */
349  { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* FMC_A5 signal */
350  { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* FMC_A6 signal */
351  { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* FMC_A7 signal */
352  { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* FMC_A8 signal */
353  { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* FMC_A9 signal */
354  { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* FMC_A10 signal */
355  { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* FMC_A11 signal */
356  },
357 #endif
358  .data = {
359  { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* FMC_D0 signal */
360  { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* FMC_D1 signal */
361  { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* FMC_D2 signal */
362  { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* FMC_D3 signal */
363  { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* FMC_D4 signal */
364  { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* FMC_D5 signal */
365  { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* FMC_D6 signal */
366  { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* FMC_D7 signal */
367 #if MODULE_PERIPH_FMC_16BIT
368  { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* FMC_D8 signal */
369  { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* FMC_D9 signal */
370  { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* FMC_D10 signal */
371  { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* FMC_D11 signal */
372  { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* FMC_D12 signal */
373  { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* FMC_D13 signal */
374  { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* FMC_D14 signal */
375  { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* FMC_D15 signal */
376 #endif
377  },
378  .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* FMC_NBL0 signal (LB) */
379  .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* FMC_NBL1 signal (UB) */
380 };
381 
394  /* bank 5 is used for SDRAM */
395  {
396  .bank = FMC_BANK_5,
397  .mem_type = FMC_SDRAM,
398  .data_width = FMC_BUS_WIDTH_16BIT,
399  .address = 0xc0000000, /* Bank 5 is mapped to 0xc0000000 */
400  .size = MiB(8), /* Size in MByte, 4M x 16 Bit */
401  .sdram = {
402  .clk_period = 2, /* SDCLK = 2 x HCLK */
403  .row_bits = 12, /* A11..A0 used for row address */
404  .col_bits = 8, /* A7..A0 used for column address */
405  .cas_latency = 2, /* CAS latency is 2 clock cycles */
406  .read_delay = 0, /* No read delay after CAS */
407  .burst_read = true, /* Burst read mode enabled */
408  .burst_write = false, /* Burst write mode disabled */
409  .burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 */
410  .burst_interleaved = false, /* Burst mode interleaved */
411  .write_protect = false, /* No write protection */
412  .four_banks = true, /* SDRAM has four internal banks */
413  .timing = { /* SDRAM Timing parameters */
414  .row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
415  .row_precharge = 2, /* Row precharge delay (2 clock cycles) */
416  .recovery_delay = 2, /* Recovery delay is (2 clock cycles) */
417  .row_cylce = 7, /* Row cycle delay is (7 clock cycles) */
418  .self_refresh = 4, /* Self refresh time is (4 clock cycles) */
419  .exit_self_refresh = 7, /* Exit self-refresh delay (7 clock cycles) */
420  .load_mode_register = 2, /* Load Mode Register to Activate delay */
421  .refresh_period = 16, /* Refresh period in ms */
422  },
423  },
424  },
425 };
426 
430 #define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
441 static const sdmmc_conf_t sdmmc_config[] = {
442  {
443  .dev = SDMMC1,
444  .bus = APB2,
445  .rcc_mask = RCC_APB2ENR_SDMMC1EN,
446  .cd = GPIO_PIN(PORT_C, 13),
447  .cd_active = 0, /* CD pin is LOW active */
448  .cd_mode = GPIO_IN_PU, /* Pull-up R12 not soldered by default */
449  .clk = { GPIO_PIN(PORT_C, 12), GPIO_AF12 },
450  .cmd = { GPIO_PIN(PORT_D, 2), GPIO_AF12 },
451  .dat0 = { GPIO_PIN(PORT_C, 8), GPIO_AF12 },
452  .dat1 = { GPIO_PIN(PORT_C, 9), GPIO_AF12 },
453  .dat2 = { GPIO_PIN(PORT_C, 10), GPIO_AF12 },
454  .dat3 = { GPIO_PIN(PORT_C, 11), GPIO_AF12 },
455 #ifdef MODULE_PERIPH_DMA
456  .dma = 5,
457  .dma_chan = 4,
458 #endif
459  .irqn = SDMMC1_IRQn
460  },
461 };
462 
466 #define SDMMC_CONFIG_NUMOF 1
467 
470 #ifdef __cplusplus
471 }
472 #endif
473 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_F
port F
Definition: periph_cpu.h:51
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
@ PORT_K
port K
Definition: periph_cpu.h:53
@ PORT_H
port H
Definition: periph_cpu.h:51
@ PORT_J
port J
Definition: periph_cpu.h:52
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const sdmmc_conf_t sdmmc_config[]
SDIO/SDMMC static configuration struct.
Definition: periph_conf.h:441
static const ltdc_conf_t ltdc_config
LTDC static configuration struct.
Definition: periph_conf.h:222
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG HS configuration with ULPI HS PHY.
Definition: periph_conf.h:292
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
Definition: periph_conf.h:393
static const fmc_conf_t fmc_config
FMC controller configuration.
Definition: periph_conf.h:331
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition: cpu_eth.h:36
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF10
use alternate function 10
Definition: cpu_gpio.h:112
@ GPIO_AF9
use alternate function 9
Definition: cpu_gpio.h:111
@ GPIO_AF14
use alternate function 14
Definition: cpu_gpio.h:116
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:114
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ FMC_SDRAM
SDRAM Controller used.
Definition: cpu_fmc.h:344
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition: cpu_fmc.h:352
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition: mii.h:68
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition: mii.h:72
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
Interface definition for MII/RMII h.
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
USB OTG configuration.
uintptr_t periph
USB peripheral base address.
Ethernet Peripheral configuration.
Definition: cpu_eth.h:43
eth_mode_t mode
Select configuration mode.
Definition: cpu_eth.h:44
Bank configuration structure.
Definition: cpu_fmc.h:359
fmc_bank_t bank
Bank1 .
Definition: cpu_fmc.h:360
FMC peripheral configuration.
Definition: cpu_fmc.h:277
uint8_t bus
AHB/APB bus.
Definition: cpu_fmc.h:278
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
LTDC Peripheral configuration.
Definition: cpu_ltdc.h:40
uint8_t bus
APB bus.
Definition: cpu_ltdc.h:41
SDMMC slot configuration.
Definition: periph_cpu.h:700
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218
#define MiB(x)
A macro to return the bytes in x MiB.
Definition: units.h:33
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_ULPI
ULPI for external HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.