periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2018 Inria
3  * 2023 Gunar Schorcht
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
23 /* Add specific clock configuration (HSE, LSE) for this board here */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
28 #include "periph_cpu.h"
29 #include "clk_conf.h"
30 #include "cfg_rtt_default.h"
31 #include "cfg_usb_otg_fs.h"
32 #include "lcd_fmc.h"
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
42 static const dma_conf_t dma_config[] = {
43  { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX */
44  { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
45  { .stream = 3 }, /* DMA1 Channel 4 - SPI2_RX / USART1_TX */
46  { .stream = 4 }, /* DMA1 Channel 5 - SPI2_TX */
47  { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
48  { .stream = 13 }, /* DMA2 Channel 6 - LPUART1_TX */
49  { .stream = 11 }, /* DMA2 Channel 4 - SDMMC1 */
50 };
51 
52 #define DMA_0_ISR isr_dma1_channel2
53 #define DMA_1_ISR isr_dma1_channel3
54 #define DMA_2_ISR isr_dma1_channel4
55 #define DMA_3_ISR isr_dma1_channel5
56 #define DMA_4_ISR isr_dma1_channel7
57 #define DMA_5_ISR isr_dma2_channel6
58 #define DMA_6_ISR isr_dma2_channel4
59 
60 #define DMA_NUMOF ARRAY_SIZE(dma_config)
99 static const adc_conf_t adc_config[] = {
100  { .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 13 }, /* A0, ADC12_IN13 */
101  { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* A1, ADC123_IN2 */
102  { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 4 }, /* A2, ADC123_IN4 */
103  { .pin = GPIO_PIN(PORT_F, 10), .dev = 2, .chan = 13 }, /* A3, ADC3_IN13 */
104  { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 6 }, /* A4, ADC12_IN6, SB26 closed */
105  { .pin = GPIO_PIN(PORT_C, 0), .dev = 1, .chan = 13 }, /* A5, ADC12_IN13, SB28 closed */
106  { .pin = GPIO_UNDEF, .dev = 0, .chan = 0 }, /* V_REFINT, ADC1_IN0 */
107  { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* V_BAT, ADC1_IN18 */
108 #if !MODULE_PERIPH_DAC
109  { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 9 }, /* STMOD+_ADC, ADC12_IN9 */
110 #else
111  { .pin = GPIO_UNDEF, .dev = 1, .chan = 17 }, /* DAC1, ADC2_IN17 */
112 #endif
113 };
114 
118 #define ADC_NUMOF ARRAY_SIZE(adc_config)
119 
123 #define VBAT_ADC ADC_LINE(7)
124 
128 #define VREFINT_ADC ADC_LINE(6)
129 
138 #ifndef VREFBUF_ENABLE
139 #define VREFBUF_ENABLE (1)
140 #endif
141 
153 static const dac_conf_t dac_config[] = {
154  { GPIO_PIN(PORT_A, 4), .chan = 0 }, /* STMod+_ADC pin */
155 #if !MODULE_PERIPH_SPI
156  { GPIO_PIN(PORT_A, 5), .chan = 1 }, /* Arduino D13, conflicts with SPI_DEV(0) */
157 #endif
158 };
159 
163 #define DAC_NUMOF ARRAY_SIZE(dac_config)
174 static const fmc_conf_t fmc_config = {
175  .bus = AHB3,
176  .rcc_mask = RCC_AHB3ENR_FMCEN,
177 #if MODULE_PERIPH_FMC_NOR_SRAM
178  .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 1 */
179  .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* PSRAM_NE signal, subbank 2 */
180  .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* PSRAM/LCD_OE signal (OE) */
181  .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* PSRAM/LCD_WE signal (WE) */
182  .addr = {
183  { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 signal */
184  { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
185  { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
186  { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
187  { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
188  { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
189  { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
190  { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
191  { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
192  { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
193  { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
194  { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
195  { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
196  { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
197  { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
198  { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
199  { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
200  { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
201  { .pin = GPIO_PIN(PORT_D, 13), .af = GPIO_AF12, }, /* PSRAM_A18 / LCD_RS signal */
202  },
203 #endif
204  .data = {
205  { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* PSRAM_D0 / LCD_D0 signal */
206  { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* PSRAM_D1 / LCD_D1 signal */
207  { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* PSRAM_D2 / LCD_D2 signal */
208  { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* PSRAM_D3 / LCD_D3 signal */
209  { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* PSRAM_D4 / LCD_D4 signal */
210  { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* PSRAM_D5 / LCD_D5 signal */
211  { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* PSRAM_D6 / LCD_D6 signal */
212  { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* PSRAM_D7 / LCD_D7 signal */
213 #if MODULE_PERIPH_FMC_16BIT
214  { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* PSRAM_D8 / LCD_D8 signal */
215  { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* PSRAM_D9 / LCD_D9 signal */
216  { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* PSRAM_D10 / LCD_D10 signal */
217  { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* PSRAM_D11 / LCD_D11 signal */
218  { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* PSRAM_D12 / LCD_D12 signal */
219  { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* PSRAM_D13 / LCD_D13 signal */
220  { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* PSRAM_D14 / LCD_D14 signal */
221  { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* PSRAM_D15 / LCD_D15 signal */
222 #endif
223  },
224  .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
225  .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
226 };
227 
239  /* bank 1, subbank 2 is used for PSRAM with asynchronuous
240  * access in Mode 1, i.e. write timings are not used */
241  {
242  .bank = FMC_BANK_1,
243  .mem_type = FMC_SRAM,
244  .data_width = FMC_BUS_WIDTH_16BIT,
245  .address = 0x64000000, /* Bank 1, subbank 2 is mapped to 0x64000000 */
246  .size = MiB(1), /* Size in Mbyte, 512K x 16 bit */
247  .nor_sram = {
248  .sub_bank = 2,
249  .ext_mode = false, /* Mode 1 used, no separate w_timing */
250  /* timings for IS66WV51216EBLL-70BLI */
251  .r_timing = { .addr_setup = 6, /* t_AA = 70 ns (6 HCLKs a 12.5 ns) */
252  .data_setup = 2, /* t_SD = 30 ns (3 HCLKs a 12.5 ns) */
253  .bus_turnaround = 1, }, /* 1 HCLK a 12.5 ns */
254  },
255  },
256  /* bank 1, subbank 1 is used for LCD with asynchronuous
257  * access in Mode 1, i.e. write timings are not used */
258  {
259  .bank = FMC_BANK_1,
260  .mem_type = FMC_SRAM,
261  .data_width = FMC_BUS_WIDTH_16BIT,
262  .address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
263  .size = 2, /* 1 word for command @ 0x60000000 and
264  1 word for data @ 0x60080000 */
265  .nor_sram = {
266  .sub_bank = 1,
267  .ext_mode = false, /* Mode 1 used, no separate w_timing */
268  /* timing requirements for ST7789H2:
269  - t_AST min 0 ns (Address setup time)
270  - t_DST min 10 ns (Data setup time)
271  - t_WRL min 15 ns (WE LOW time)
272  - t_WRH min 15 ns (WE HIGH time)
273  - t_WRC min 66 ns (WE cycle time) */
274  .r_timing = { .addr_setup = 1, /* t_AST = 12 ns (1 HCLKs a 12.5 ns) */
275  .data_setup = 3, /* t_DST = 37 ns (3 HCLKs a 12.5 ns) */
276  .bus_turnaround = 2, }, /* t_WRH = 25 ns (2 HCLKs a 12.5 ns) */
277  },
278  },
279 };
280 
284 #define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
285 
289 static const lcd_fmc_desc_t lcd_fmc_desc[] = {
290  {
291  .bank = FMC_BANK_CONFIG(1), /* second bank (fmc_bank_config[1]) is used */
292  .cmd_offset = 0x0, /* address 0x60000000 (offset 0x00000) used for commands */
293  .data_offset = 0x80000, /* address 0x60080000 (offset 0x80000) used for data */
294  }
295 };
296 
303 #define LCD_FMC_NUMOF 1
304 
314 static const i2c_conf_t i2c_config[] = {
315  { /* Shared between Arduino D14/D15 and STMod+ connector */
316  .dev = I2C1,
317  .speed = I2C_SPEED_NORMAL,
318  .scl_pin = GPIO_PIN(PORT_B, 8),
319  .sda_pin = GPIO_PIN(PORT_B, 7),
320  .scl_af = GPIO_AF4,
321  .sda_af = GPIO_AF4,
322  .bus = APB1,
323  .rcc_mask = RCC_APB1ENR1_I2C1EN,
324  .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
325  .irqn = I2C1_ER_IRQn,
326  },
327  { /* Multi Function eXpander (MFX_x) I2C Address 0x42,
328  * Stereo Codec Cirrus Logic CS42L51-CNZ (CODEC_x), I2C Address 0x4a (AD0 = 0)
329  * Capacitive Touch Panel (CTP_x) FT6206, I2C Address 0x38
330  * Digital Camera Module (DCMI_x),
331  */
332  .dev = I2C2,
333  .speed = I2C_SPEED_NORMAL,
334  .scl_pin = GPIO_PIN(PORT_H, 4),
335  .sda_pin = GPIO_PIN(PORT_B, 14),
336  .scl_af = GPIO_AF4,
337  .sda_af = GPIO_AF4,
338  .bus = APB1,
339  .rcc_mask = RCC_APB1ENR1_I2C2EN,
340  .rcc_sw_mask = RCC_CCIPR_I2C2SEL_1, /* HSI (16 MHz) */
341  .irqn = I2C2_ER_IRQn,
342  },
343 };
344 
345 #define I2C_0_ISR isr_i2c1_er
346 #define I2C_1_ISR isr_i2c2_er
347 
348 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
363 static const pwm_conf_t pwm_config[] = {
364  {
365  .dev = TIM8,
366  .rcc_mask = RCC_APB2ENR_TIM8EN,
367  .chan = { { .pin = GPIO_PIN(PORT_H, 15), .cc_chan = 6}, /* D3, TIM8_CH3N */
368  { .pin = GPIO_PIN(PORT_I, 6), .cc_chan = 1}, /* D6, TIM8_CH2 */
369  { .pin = GPIO_PIN(PORT_H, 13), .cc_chan = 4}, /* D9, TIM8_CH1N */
370  { .pin = GPIO_UNDEF, .cc_chan = 0} },
371  .af = GPIO_AF3,
372  .bus = APB2
373  },
374  {
375  .dev = TIM4,
376  .rcc_mask = RCC_APB1ENR1_TIM4EN,
377  .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 3}, /* D5, TIM4_CH4 */
378  { .pin = GPIO_UNDEF, .cc_chan = 0},
379  { .pin = GPIO_UNDEF, .cc_chan = 0},
380  { .pin = GPIO_UNDEF, .cc_chan = 0} },
381  .af = GPIO_AF2,
382  .bus = APB1
383  },
384  {
385  .dev = TIM5,
386  .rcc_mask = RCC_APB1ENR1_TIM5EN,
387  .chan = { { .pin = GPIO_PIN(PORT_A, 0), .cc_chan = 0}, /* STMOD+_PWM, TIM5_CH1 */
388  { .pin = GPIO_UNDEF, .cc_chan = 0},
389  { .pin = GPIO_UNDEF, .cc_chan = 0},
390  { .pin = GPIO_UNDEF, .cc_chan = 0} },
391  .af = GPIO_AF2,
392  .bus = APB1
393  },
394 };
395 
396 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
407 static const sdmmc_conf_t sdmmc_config[] = {
408  {
409  .dev = SDMMC1,
410  .bus = APB2,
411  .rcc_mask = RCC_APB2ENR_SDMMC1EN,
412  .cd = GPIO_UNDEF, /* CD is connected to MFX GPIO8 */
413  .clk = { GPIO_PIN(PORT_C, 12), GPIO_AF12 },
414  .cmd = { GPIO_PIN(PORT_D, 2), GPIO_AF12 },
415  .dat0 = { GPIO_PIN(PORT_C, 8), GPIO_AF12 },
416  .dat1 = { GPIO_PIN(PORT_C, 9), GPIO_AF12 },
417  .dat2 = { GPIO_PIN(PORT_C, 10), GPIO_AF12 },
418  .dat3 = { GPIO_PIN(PORT_C, 11), GPIO_AF12 },
419 #if MODULE_PERIPH_DMA
420  .dma = 6,
421  .dma_chan = 7,
422 #endif
423  .irqn = SDMMC1_IRQn
424  },
425 };
426 
430 #define SDMMC_CONFIG_NUMOF 1
431 
446 static const spi_conf_t spi_config[] = {
447  { /* Arduino connector */
448  .dev = SPI1,
449  .mosi_pin = GPIO_PIN(PORT_B, 5),
450  .miso_pin = GPIO_PIN(PORT_B, 4),
451  .sclk_pin = GPIO_PIN(PORT_A, 5),
452  .cs_pin = GPIO_PIN(PORT_A, 15),
453  .mosi_af = GPIO_AF5,
454  .miso_af = GPIO_AF5,
455  .sclk_af = GPIO_AF5,
456  .cs_af = GPIO_AF5,
457  .rccmask = RCC_APB2ENR_SPI1EN,
458  .apbbus = APB2,
459 #if MODULE_PERIPH_DMA
460  .rx_dma = 0, /* DMA1 Channel 2 */
461  .rx_dma_chan = 1, /* CxS = 1 */
462  .tx_dma = 1, /* DMA1 Channel 3 */
463  .tx_dma_chan = 1, /* CxS = 1 */
464 #endif
465  },
466 #if MODULE_PERIPH_SPI_STMOD
467  { /* Pmod/STMod+ connector if solder bridges SB4, SB5, SB9 are closed */
468  .dev = SPI2,
469  .mosi_pin = GPIO_PIN(PORT_B, 15),
470  .miso_pin = GPIO_PIN(PORT_I, 2),
471  .sclk_pin = GPIO_PIN(PORT_I, 1),
472  .cs_pin = GPIO_PIN(PORT_G, 1),
473  .mosi_af = GPIO_AF5,
474  .miso_af = GPIO_AF5,
475  .sclk_af = GPIO_AF5,
476  .cs_af = GPIO_AF5,
477  .rccmask = RCC_APB1ENR1_SPI2EN,
478  .apbbus = APB1,
479 #if MODULE_PERIPH_DMA
480  .rx_dma = 2, /* DMA1 Channel 4 */
481  .rx_dma_chan = 1, /* CxS = 1 */
482  .tx_dma = 3, /* DMA1 Channel 5 */
483  .tx_dma_chan = 1, /* CxS = 1 */
484 #endif
485  },
486 #endif
487 };
488 
489 #define SPI_NUMOF ARRAY_SIZE(spi_config)
496 static const timer_conf_t timer_config[] = {
497  {
498  .dev = TIM2,
499  .max = 0xffffffff,
500  .rcc_mask = RCC_APB1ENR1_TIM2EN,
501  .bus = APB1,
502  .irqn = TIM2_IRQn
503  },
504  {
505  .dev = TIM3,
506  .max = 0xffffffff,
507  .rcc_mask = RCC_APB1ENR1_TIM3EN,
508  .bus = APB1,
509  .irqn = TIM3_IRQn
510  },
511 };
512 
513 #define TIMER_0_ISR isr_tim2
514 #define TIMER_1_ISR isr_tim3
515 
516 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
530 static const uart_conf_t uart_config[] = {
531  { /* Virtual COM Port / ST-Link */
532  .dev = USART2,
533  .rcc_mask = RCC_APB1ENR1_USART2EN,
534  .rx_pin = GPIO_PIN(PORT_D, 6),
535  .tx_pin = GPIO_PIN(PORT_A, 2),
536  .rx_af = GPIO_AF7,
537  .tx_af = GPIO_AF7,
538  .bus = APB1,
539  .irqn = USART2_IRQn,
540 #if MODULE_PERIPH_UART_HW_FC
541  .cts_pin = GPIO_UNDEF, /* CTS is not connected */
542  .rts_pin = GPIO_UNDEF, /* RTS is not connected */
543 #endif
544  .type = STM32_USART,
545  .clk_src = 0, /* Use APB clock */
546 #if MODULE_PERIPH_DMA
547  .dma = 4, /* DMA1 Channel 7 */
548  .dma_chan = 2, /* CxS = 2 */
549 #endif
550  },
551  { /* Arduino connector RX/TX (D0/D1) */
552  .dev = LPUART1,
553  .rcc_mask = RCC_APB1ENR2_LPUART1EN,
554  .rx_pin = GPIO_PIN(PORT_G, 8),
555  .tx_pin = GPIO_PIN(PORT_G, 7),
556  .rx_af = GPIO_AF8,
557  .tx_af = GPIO_AF8,
558  .bus = APB12,
559  .irqn = LPUART1_IRQn,
560 #if MODULE_PERIPH_UART_HW_FC
561  .cts_pin = GPIO_UNDEF, /* CTS is not connected */
562  .rts_pin = GPIO_UNDEF, /* RTS is not connected */
563 #endif
564  .type = STM32_LPUART,
565  .clk_src = 0, /* Use APB clock */
566 #if MODULE_PERIPH_DMA
567  .dma = 5, /* DMA2 Channel 6 */
568  .dma_chan = 4, /* CxS = 4 */
569 #endif
570  },
571 
572 #if !MODULE_PERIPH_SPI_STMOD
573  { /* Pmod/STMod+ connector if solder bridges SB6, SB7, SB8 are closed (default) */
574  .dev = USART1,
575  .rcc_mask = RCC_APB2ENR_USART1EN,
576  .rx_pin = GPIO_PIN(PORT_G, 10),
577  .tx_pin = GPIO_PIN(PORT_B, 6),
578  .rx_af = GPIO_AF7,
579  .tx_af = GPIO_AF7,
580  .bus = APB2,
581  .irqn = USART1_IRQn,
582 #if MODULE_PERIPH_UART_HW_FC
583  .cts_pin = GPIO_PIN(PORT_G, 11),
584  .rts_pin = GPIO_PIN(PORT_G, 12),
585  .cts_af = GPIO_AF7,
586  .rts_af = GPIO_AF7,
587 #endif
588  .type = STM32_USART,
589  .clk_src = 0, /* Use APB clock */
590 #if MODULE_PERIPH_DMA
591  .dma = 2, /* DMA1 Channel 4 */
592  .dma_chan = 2, /* CxS = 2 */
593 #endif
594  },
595 #endif /* !MODULE_PERIPH_SPI_STMOD */
596 };
597 
598 #define UART_0_ISR (isr_usart2)
599 #define UART_1_ISR (isr_lpuart1)
600 #define UART_2_ISR (isr_usart1)
601 
602 #define UART_NUMOF ARRAY_SIZE(uart_config)
605 #ifdef __cplusplus
606 }
607 #endif
608 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_F
port F
Definition: periph_cpu.h:51
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
@ PORT_H
port H
Definition: periph_cpu.h:51
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
static const dac_conf_t dac_config[]
DAC configuration.
Definition: periph_conf.h:252
static const sdmmc_conf_t sdmmc_config[]
SDIO/SDMMC static configuration struct.
Definition: periph_conf.h:407
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Definition: periph_conf.h:289
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
Definition: periph_conf.h:238
static const fmc_conf_t fmc_config
FMC controller configuration.
Definition: periph_conf.h:174
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF3
use alternate function 3
Definition: cpu_gpio.h:104
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:114
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: cpu_uart.h:38
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:37
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
Definition: cpu_fmc.h:74
@ FMC_SRAM
SRAM.
Definition: cpu_fmc.h:340
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition: cpu_fmc.h:352
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
Definition: cpu_fmc.h:320
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
ADC device configuration.
Definition: periph_cpu.h:377
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:287
DAC line configuration data.
Definition: periph_cpu.h:300
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
Bank configuration structure.
Definition: cpu_fmc.h:359
fmc_bank_t bank
Bank1 .
Definition: cpu_fmc.h:360
FMC peripheral configuration.
Definition: cpu_fmc.h:277
uint8_t bus
AHB/APB bus.
Definition: cpu_fmc.h:278
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
Descriptor of the FMC bank used for a LCD.
Definition: lcd_fmc.h:48
const fmc_bank_conf_t * bank
FMC bank config used for the LCD.
Definition: lcd_fmc.h:49
PWM device configuration.
mini_timer_t * dev
Timer used.
SDMMC slot configuration.
Definition: periph_cpu.h:700
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218
#define MiB(x)
A macro to return the bytes in x MiB.
Definition: units.h:33