periph_cpu_common.h
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1 /*
2  * Copyright (C) 2025 Mesotic SAS
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
22 #include "cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 #ifndef DOXYGEN
29 #define HAVE_GPIO_T
30 typedef uint32_t gpio_t;
31 
32 #define GPIO_UNDEF (0xffffffff)
33 
34 #define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
35 #endif /* DOXYGEN */
36 
45 #define TIMER_CHANNEL_NUMOF (1)
46 
55 #define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
56 
57 #ifndef DOXYGEN
58 #define HAVE_GPIO_MODE_T
59 typedef enum {
60  GPIO_IN = GPIO_MODE(0, 0, 0),
61  GPIO_IN_PD = 0xf,
62  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
63  GPIO_OUT = GPIO_MODE(1, 0, 0),
64  GPIO_OD = GPIO_MODE(1, 0, 1),
65  GPIO_OD_PU = GPIO_MODE(1, 1, 1),
66 } gpio_mode_t;
67 
68 #define HAVE_GPIO_FLANK_T
69 typedef enum {
70  GPIO_RISING = 1,
71  GPIO_FALLING = 2,
72  GPIO_BOTH = 3
73 } gpio_flank_t;
74 #endif /* ndef DOXYGEN */
75 
79 typedef enum {
80  GPIO_MUX_A = 0,
81  GPIO_MUX_B = 1,
82 #ifdef CPU_FAM_SAM4S
83  GPIO_MUX_C = 2,
84  GPIO_MUX_D = 3,
85 #endif
86 } gpio_mux_t;
87 
91 enum {
92  PA = 0,
93  PB = 1,
94  PC = 2,
95 #ifdef CPU_FAM_SAM3
96  PD = 3,
97 #endif
98 };
99 
106 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
107 
111 typedef struct {
112  Tc *dev;
113  uint8_t id_ch0;
114 } timer_conf_t;
115 
119 typedef struct {
120  Uart *dev;
121  gpio_t rx_pin;
122  gpio_t tx_pin;
123  gpio_mux_t mux;
124  uint8_t pmc_id;
125  uint8_t irqn;
126 } uart_conf_t;
127 
128 #ifdef __cplusplus
129 }
130 #endif
131 
@ GPIO_OUT
select GPIO MASK as output
Definition: periph_cpu.h:164
@ GPIO_IN
select GPIO MASK as input
Definition: periph_cpu.h:163
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:91
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
@ GPIO_FALLING
emit interrupt on falling flank
@ GPIO_RISING
emit interrupt on rising flank
@ GPIO_BOTH
not supported -> random value
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
gpio_flank_t
Enumeration of supported GPIO flanks.
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_A
select peripheral function A
@ GPIO_MUX_B
select peripheral function B
#define GPIO_MODE(io, pu, od)
Generate GPIO mode bitfields.
Timer device configuration.
Definition: periph_cpu.h:263
Tc * dev
timer device
uint8_t id_ch0
ID of the timer's first channel.
UART device configuration.
Definition: periph_cpu.h:217
uint8_t pmc_id
bit in the PMC register of the device
Uart * dev
U(S)ART device used.