periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  * 2019 Freie Universität Berln
4  * 2019 Kaspar Schleiser <kaspar@schleiser.de>
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
11 #pragma once
12 
23 /* This board provides an LSE */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
28 /* This board provides an HSE */
29 #ifndef CONFIG_BOARD_HAS_HSE
30 #define CONFIG_BOARD_HAS_HSE 1
31 #endif
32 
33 /* The HSE provides a 12MHz clock */
34 #ifndef CONFIG_CLOCK_HSE
35 #define CONFIG_CLOCK_HSE MHZ(12)
36 #endif
37 
38 #include "periph_cpu.h"
39 #include "clk_conf.h"
40 #include "cfg_usb_otg_fs.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
50 static const dma_conf_t dma_config[] = {
51  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
52  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
53 };
54 
55 #define DMA_0_ISR isr_dma2_stream3
56 #define DMA_1_ISR isr_dma2_stream2
57 
58 #define DMA_NUMOF ARRAY_SIZE(dma_config)
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM5,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM5EN,
70  .bus = APB1,
71  .irqn = TIM5_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim5
76 
77 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = USART1,
87  .rcc_mask = RCC_APB2ENR_USART1EN,
88  .rx_pin = GPIO_PIN(PORT_B, 7),
89  .tx_pin = GPIO_PIN(PORT_B, 6),
90  .rx_af = GPIO_AF7,
91  .tx_af = GPIO_AF7,
92  .bus = APB2,
93  .irqn = USART1_IRQn,
94 #ifdef MODULE_PERIPH_DMA
95  .dma = DMA_STREAM_UNDEF,
96  .dma_chan = UINT8_MAX,
97 #endif
98  },
99 };
100 
101 #define UART_0_ISR (isr_usart1)
102 
103 #define UART_NUMOF ARRAY_SIZE(uart_config)
110 static const spi_conf_t spi_config[] = {
111  {
112  .dev = SPI1,
113  .mosi_pin = GPIO_PIN(PORT_A, 7),
114  .miso_pin = GPIO_PIN(PORT_A, 6),
115  .sclk_pin = GPIO_PIN(PORT_A, 5),
116  .cs_pin = GPIO_UNDEF,
117  .mosi_af = GPIO_AF5,
118  .miso_af = GPIO_AF5,
119  .sclk_af = GPIO_AF5,
120  .cs_af = GPIO_AF5,
121  .rccmask = RCC_APB2ENR_SPI1EN,
122  .apbbus = APB2,
123 #ifdef MODULE_PERIPH_DMA
124  .tx_dma = 0,
125  .tx_dma_chan = 3,
126  .rx_dma = 1,
127  .rx_dma_chan = 3,
128 #endif
129  }
130 };
131 
132 #define SPI_NUMOF ARRAY_SIZE(spi_config)
139 static const i2c_conf_t i2c_config[] = {
140  {
141  .dev = I2C2,
142  .speed = I2C_SPEED_NORMAL,
143  .scl_pin = GPIO_PIN(PORT_B, 10),
144  .sda_pin = GPIO_PIN(PORT_B, 11),
145  .scl_af = GPIO_AF4,
146  .sda_af = GPIO_AF4,
147  .bus = APB1,
148  .rcc_mask = RCC_APB1ENR_I2C2EN,
149  .clk = CLOCK_APB1,
150  .irqn = I2C2_ER_IRQn,
151  },
152 };
153 
154 #define I2C_0_ISR isr_i2c2_er
155 
156 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
159 #ifdef __cplusplus
160 }
161 #endif
162 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
#define CLOCK_APB1
Half AHB clock.
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218