periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 /* This board provides an LSE */
22 #ifndef CONFIG_BOARD_HAS_LSE
23 #define CONFIG_BOARD_HAS_LSE 1
24 #endif
25 
26 /* This board provides an HSE */
27 #ifndef CONFIG_BOARD_HAS_HSE
28 #define CONFIG_BOARD_HAS_HSE 1
29 #endif
30 
31 /* The HSE provides a 25MHz clock */
32 #ifndef CONFIG_CLOCK_HSE
33 #define CONFIG_CLOCK_HSE MHZ(25)
34 #endif
35 
36 #include "periph_cpu.h"
37 #include "clk_conf.h"
38 #include "cfg_rtt_default.h"
39 #if defined(MODULE_PERIPH_USBDEV_HS_UTMI)
41 #else
42 #include "cfg_usb_otg_fs.h"
43 #endif
44 #include "lcd_fmc.h"
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
54 static const timer_conf_t timer_config[] = {
55  {
56  .dev = TIM2,
57  .max = 0xffffffff,
58  .rcc_mask = RCC_APB1ENR_TIM2EN,
59  .bus = APB1,
60  .irqn = TIM2_IRQn
61  }
62 };
63 
64 #define TIMER_0_ISR isr_tim2
65 
66 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
73 static const uart_conf_t uart_config[] = {
74  {
75  .dev = USART6,
76  .rcc_mask = RCC_APB2ENR_USART6EN,
77  .rx_pin = GPIO_PIN(PORT_C, 6),
78  .tx_pin = GPIO_PIN(PORT_C, 7),
79  .rx_af = GPIO_AF8,
80  .tx_af = GPIO_AF8,
81  .bus = APB2,
82  .irqn = USART6_IRQn,
83 #ifdef MODULE_PERIPH_UART_HW_FC
84  .cts_pin = GPIO_UNDEF,
85  .rts_pin = GPIO_UNDEF,
86  .cts_af = GPIO_AF8,
87  .rts_af = GPIO_AF8,
88 #endif
89  },
90  { /* Arduino connector (D0/D1) */
91  .dev = USART2,
92  .rcc_mask = RCC_APB1ENR_USART2EN,
93  .rx_pin = GPIO_PIN(PORT_A, 3),
94  .tx_pin = GPIO_PIN(PORT_A, 2),
95  .rx_af = GPIO_AF7,
96  .tx_af = GPIO_AF7,
97  .bus = APB1,
98  .irqn = USART2_IRQn,
99 #ifdef MODULE_PERIPH_UART_HW_FC
100  .cts_pin = GPIO_UNDEF,
101  .rts_pin = GPIO_UNDEF,
102  .cts_af = GPIO_AF8,
103  .rts_af = GPIO_AF8,
104 #endif
105  },
106  { /* PMOD connector */
107  .dev = UART7,
108  .rcc_mask = RCC_APB1ENR_UART7EN,
109  .rx_pin = GPIO_PIN(PORT_F, 6),
110  .tx_pin = GPIO_PIN(PORT_F, 7),
111  .rx_af = GPIO_AF8,
112  .tx_af = GPIO_AF8,
113  .bus = APB1,
114  .irqn = UART7_IRQn,
115 #ifdef MODULE_PERIPH_UART_HW_FC
116  .cts_pin = GPIO_PIN(PORT_F, 9),
117  .rts_pin = GPIO_PIN(PORT_F, 8),
118  .cts_af = GPIO_AF8,
119  .rts_af = GPIO_AF8,
120 #endif
121  },
122  { /* ESP-01 connector */
123  .dev = UART5,
124  .rcc_mask = RCC_APB1ENR_UART5EN,
125  .rx_pin = GPIO_PIN(PORT_D, 2),
126  .tx_pin = GPIO_PIN(PORT_C, 12),
127  .rx_af = GPIO_AF8,
128  .tx_af = GPIO_AF8,
129  .bus = APB1,
130  .irqn = UART5_IRQn,
131 #ifdef MODULE_PERIPH_UART_HW_FC
132  .cts_pin = GPIO_UNDEF,
133  .rts_pin = GPIO_UNDEF,
134  .cts_af = GPIO_AF8,
135  .rts_af = GPIO_AF8,
136 #endif
137  },
138 };
139 
140 #define UART_0_ISR (isr_usart6)
141 #define UART_1_ISR (isr_usart2)
142 #define UART_2_ISR (isr_uart4)
143 #define UART_3_ISR (isr_uart7)
144 #define UART_4_ISR (isr_uart5)
145 
146 #define UART_NUMOF ARRAY_SIZE(uart_config)
153 static const i2c_conf_t i2c_config[] = {
154  { /* Shared between Arduino D14/D15 and STMOD+ connector */
155  .dev = I2C2,
156  .speed = I2C_SPEED_NORMAL,
157  .scl_pin = GPIO_PIN(PORT_H, 4),
158  .sda_pin = GPIO_PIN(PORT_H, 5),
159  .scl_af = GPIO_AF4,
160  .sda_af = GPIO_AF4,
161  .bus = APB1,
162  .rcc_mask = RCC_APB1ENR_I2C2EN,
163  .rcc_sw_mask = RCC_DCKCFGR2_I2C2SEL_1,
164  .irqn = I2C2_ER_IRQn,
165  },
166  { /* Connected to touchscreen controller */
167  .dev = I2C3,
168  .speed = I2C_SPEED_NORMAL,
169  .scl_pin = GPIO_PIN(PORT_A, 8),
170  .sda_pin = GPIO_PIN(PORT_H, 8),
171  .scl_af = GPIO_AF4,
172  .sda_af = GPIO_AF4,
173  .bus = APB1,
174  .rcc_mask = RCC_APB1ENR_I2C3EN,
175  .rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
176  .irqn = I2C3_ER_IRQn,
177  },
178  {
179  .dev = I2C1,
180  .speed = I2C_SPEED_NORMAL,
181  .scl_pin = GPIO_PIN(PORT_B, 8),
182  .sda_pin = GPIO_PIN(PORT_B, 9),
183  .scl_af = GPIO_AF4,
184  .sda_af = GPIO_AF4,
185  .bus = APB1,
186  .rcc_mask = RCC_APB1ENR_I2C1EN,
187  .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
188  .irqn = I2C1_ER_IRQn,
189  },
190 };
191 
192 #define I2C_0_ISR isr_i2c2_er
193 #define I2C_1_ISR isr_i2c3_er
194 #define I2C_2_ISR isr_i2c1_er
195 
196 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
203 static const spi_conf_t spi_config[] = {
204  { /* Arduino connector */
205  .dev = SPI1,
206  .mosi_pin = GPIO_PIN(PORT_B, 5),
207  .miso_pin = GPIO_PIN(PORT_B, 4),
208  .sclk_pin = GPIO_PIN(PORT_A, 5),
209  .cs_pin = SPI_CS_UNDEF,
210  .mosi_af = GPIO_AF5,
211  .miso_af = GPIO_AF5,
212  .sclk_af = GPIO_AF5,
213  .cs_af = GPIO_AF5,
214  .rccmask = RCC_APB2ENR_SPI1EN,
215  .apbbus = APB2
216  },
217  { /* PMOD connector */
218  .dev = SPI2,
219  .mosi_pin = GPIO_PIN(PORT_I, 3),
220  .miso_pin = GPIO_PIN(PORT_I, 2),
221  .sclk_pin = GPIO_PIN(PORT_I, 1),
222  .cs_pin = GPIO_PIN(PORT_I, 0),
223  .mosi_af = GPIO_AF5,
224  .miso_af = GPIO_AF5,
225  .sclk_af = GPIO_AF5,
226  .cs_af = GPIO_AF5,
227  .rccmask = RCC_APB1ENR_SPI2EN,
228  .apbbus = APB1
229  },
230 };
231 
232 #define SPI_NUMOF ARRAY_SIZE(spi_config)
243 static const fmc_conf_t fmc_config = {
244  .bus = AHB3,
245  .rcc_mask = RCC_AHB3ENR_FMCEN,
246 #if MODULE_PERIPH_FMC_NOR_SRAM
247  .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* PSRAM_NE1 signal, subbank 1 */
248  .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 2 */
249  .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* LCD_PSRAM_NOE */
250  .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* LCD_PSRAM_NWE signal */
251  .addr = {
252  { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 / LCD_RS signal */
253  { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
254  { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
255  { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
256  { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
257  { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
258  { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
259  { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
260  { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
261  { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
262  { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
263  { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
264  { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
265  { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
266  { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
267  { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
268  { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
269  { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
270  },
271 #endif
272  .data = {
273  { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D0 signal */
274  { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D1 signal */
275  { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* LCD_PSRAM_D2 signal */
276  { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* LCD_PSRAM_D3 signal */
277  { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* LCD_PSRAM_D4 signal */
278  { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D5 signal */
279  { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D6 signal */
280  { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D7 signal */
281 #if MODULE_PERIPH_FMC_16BIT
282  { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* LCD_PSRAM_D8 signal */
283  { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* LCD_PSRAM_D9 signal */
284  { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* LCD_PSRAM_D10 signal */
285  { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D11 signal */
286  { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D12 signal */
287  { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D13 signal */
288  { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D14 signal */
289  { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D15 signal */
290 #endif
291  },
292  .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
293  .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
294 };
295 
310  /* bank 1, subbank 1 is used for PSRAM with asynchronuous
311  * access in Mode 1, i.e. write timings are not used */
312  {
313  .bank = FMC_BANK_1,
314  .mem_type = FMC_SRAM,
315  .data_width = FMC_BUS_WIDTH_16BIT,
316  .address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
317  .size = KiB(512), /* Size in byte, 256K x 16 bit */
318  .nor_sram = {
319  .sub_bank = 1,
320  .ext_mode = false, /* Mode 1 used, no separate w_timing */
321  /* timings for IS66WV51216EBLL-55BLI
322  @216 MHz AHB clock */
323  .r_timing = { .addr_setup = 13, /* t_AA = max 60 ns (13 HCLKs a 4.63 ns) */
324  .data_setup = 6, /* t_SD = min 25 ns (6 HCLKs a 4.63 ns) */
325  .bus_turnaround = 3, }, /* 3 HCLKs a 4.63 ns */
326  },
327  },
328  /* bank 1, subbank 2 is used for LCD with asynchronuous
329  * access in Mode 1, i.e. write timings are not used */
330  {
331  .bank = FMC_BANK_1,
332  .mem_type = FMC_SRAM,
333  .data_width = FMC_BUS_WIDTH_16BIT,
334  .address = 0x64000000, /* Bank 1, subbank 2 is mapped to 0x64000000 */
335  .size = 4, /* 1 word for command @ 0x64000000 and
336  1 word for data @ 0x64000001 */
337  .nor_sram = {
338  .sub_bank = 2,
339  .ext_mode = false, /* Mode 1 used, no separate w_timing */
340  /* timing requirements for ST7789H2:
341  - t_AST min 0 ns (Address setup time)
342  - t_DST min 10 ns (Data setup time)
343  - t_WRL min 15 ns (WE LOW time)
344  - t_WRH min 15 ns (WE HIGH time)
345  - t_WRC min 66 ns (WE cycle time) */
346  .r_timing = { .addr_setup = 2, /* t_AST = 10 ns (2 HCLKs a 4.63 ns) */
347  .data_setup = 8, /* t_DST = 37 ns (8 HCLKs a 4.63 ns) */
348  .bus_turnaround = 5, }, /* t_WRH = 23 ns (5 HCLKs a 4.63 ns) */
349  },
350  },
351 };
352 
356 #define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
362 static const lcd_fmc_desc_t lcd_fmc_desc[] = {
363  {
364  .bank = FMC_BANK_CONFIG(1), /* second bank (fmc_bank_config[1]) is used */
365  .cmd_offset = 0x0, /* address 0x64000000 (offset 0x0) used for commands */
366  .data_offset = 0x2, /* address 0x64000002 (offset 0x2) used for commands */
367  }
368 };
369 
376 #define LCD_FMC_NUMOF 1
377 
378 #ifdef __cplusplus
379 }
380 #endif
381 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_F
port F
Definition: periph_cpu.h:51
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
@ PORT_H
port H
Definition: periph_cpu.h:51
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Definition: periph_conf.h:362
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
Definition: periph_conf.h:309
static const fmc_conf_t fmc_config
FMC controller configuration.
Definition: periph_conf.h:243
Common configuration for STM32 OTG FS peripheral.
Common configuration for STM32 OTG HS peripheral with internal UTMI HS PHY.
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:114
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
Definition: cpu_fmc.h:74
@ FMC_SRAM
SRAM.
Definition: cpu_fmc.h:340
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition: cpu_fmc.h:352
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
Definition: cpu_fmc.h:320
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
Bank configuration structure.
Definition: cpu_fmc.h:359
fmc_bank_t bank
Bank1 .
Definition: cpu_fmc.h:360
FMC peripheral configuration.
Definition: cpu_fmc.h:277
uint8_t bus
AHB/APB bus.
Definition: cpu_fmc.h:278
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
Descriptor of the FMC bank used for a LCD.
Definition: lcd_fmc.h:48
const fmc_bank_conf_t * bank
FMC bank config used for the LCD.
Definition: lcd_fmc.h:49
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218
#define KiB(x)
A macro to return the bytes in x KiB.
Definition: units.h:28