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cc26xx_cc13xx_adi.h
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/*
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* SPDX-FileCopyrightText: 2020 Locha Inc
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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#include "
cc26xx_cc13xx.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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reg8_t
__reserved1
;
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reg8_t
ATESTCTL1
;
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reg8_t
REFSYSCTL0
;
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reg8_t
REFSYSCTL1
;
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reg8_t
REFSYSCTL2
;
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reg8_t
REFSYSCTL3
;
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reg8_t
DCDCCTL0
;
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reg8_t
DCDCCTL1
;
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reg8_t
DCDCCTL2
;
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reg8_t
DCDCCTL3
;
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reg8_t
DCDCCTL4
;
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reg8_t
DCDCCTL5
;
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#ifdef CPU_VARIANT_X2
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reg8_t
AUX_DEBUG;
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reg8_t
CTL_RECHARGE_CMP0;
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reg8_t
CTL_RECHARGE_CMP1;
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#endif
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}
adi_3_refsys_regs_t
;
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typedef
struct
{
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reg8_m4_t
__reserved1
;
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reg8_m4_t
ATESTCTL1
;
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reg8_m4_t
REFSYSCTL0
;
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reg8_m4_t
REFSYSCTL1
;
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reg8_m4_t
REFSYSCTL2
;
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reg8_m4_t
REFSYSCTL3
;
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reg8_m4_t
DCDCCTL0
;
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reg8_m4_t
DCDCCTL1
;
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reg8_m4_t
DCDCCTL2
;
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reg8_m4_t
DCDCCTL3
;
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reg8_m4_t
DCDCCTL4
;
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reg8_m4_t
DCDCCTL5
;
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#ifdef CPU_VARIANT_X2
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reg8_m4_t
AUX_DEBUG;
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reg8_m4_t
CTL_RECHARGE_CMP0;
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reg8_m4_t
CTL_RECHARGE_CMP1;
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#endif
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}
adi_3_refsys_regs_m4_t
;
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#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002
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#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040
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#define ADI_3_REFSYS_BASE (PERIPH_BASE + 0x86200)
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#define ADI_3_REFSYS_BASE_SET (ADI_3_REFSYS_BASE + ADI_SET)
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#define ADI_3_REFSYS_BASE_CLR (ADI_3_REFSYS_BASE + ADI_CLR)
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#define ADI_3_REFSYS_BASE_M4 (ADI_3_REFSYS_BASE + ADI_MASK4B)
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#define ADI3 ((adi_3_refsys_regs_t *) (ADI_3_REFSYS_BASE))
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#define ADI3_SET ((adi_3_refsys_regs_t *) (ADI_3_REFSYS_BASE_SET))
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#define ADI3_CLR ((adi_3_refsys_regs_t *) (ADI_3_REFSYS_BASE_CLR))
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#define ADI3_M4 ((adi_3_refsys_regs_m4_t *) (ADI_3_REFSYS_BASE_M4))
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#ifdef __cplusplus
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}
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#endif
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cc26xx_cc13xx.h
CC26xx, CC13xx definitions.
reg8_t
volatile uint8_t reg8_t
Unsigned 8-bit register type.
Definition:
cc26xx_cc13xx.h:28
adi_3_refsys_regs_m4_t
ADI_3_REFSYS registers.
Definition:
cc26xx_cc13xx_adi.h:50
adi_3_refsys_regs_m4_t::REFSYSCTL0
reg8_m4_t REFSYSCTL0
Internal.
Definition:
cc26xx_cc13xx_adi.h:53
adi_3_refsys_regs_m4_t::DCDCCTL3
reg8_m4_t DCDCCTL3
Internal.
Definition:
cc26xx_cc13xx_adi.h:60
adi_3_refsys_regs_m4_t::DCDCCTL5
reg8_m4_t DCDCCTL5
Internal.
Definition:
cc26xx_cc13xx_adi.h:62
adi_3_refsys_regs_m4_t::DCDCCTL2
reg8_m4_t DCDCCTL2
DCDC Control 2.
Definition:
cc26xx_cc13xx_adi.h:59
adi_3_refsys_regs_m4_t::REFSYSCTL1
reg8_m4_t REFSYSCTL1
Internal.
Definition:
cc26xx_cc13xx_adi.h:54
adi_3_refsys_regs_m4_t::REFSYSCTL3
reg8_m4_t REFSYSCTL3
Internal.
Definition:
cc26xx_cc13xx_adi.h:56
adi_3_refsys_regs_m4_t::__reserved1
reg8_m4_t __reserved1
Reserved.
Definition:
cc26xx_cc13xx_adi.h:51
adi_3_refsys_regs_m4_t::DCDCCTL1
reg8_m4_t DCDCCTL1
DCDC Control 1.
Definition:
cc26xx_cc13xx_adi.h:58
adi_3_refsys_regs_m4_t::REFSYSCTL2
reg8_m4_t REFSYSCTL2
Internal.
Definition:
cc26xx_cc13xx_adi.h:55
adi_3_refsys_regs_m4_t::DCDCCTL4
reg8_m4_t DCDCCTL4
Internal.
Definition:
cc26xx_cc13xx_adi.h:61
adi_3_refsys_regs_m4_t::ATESTCTL1
reg8_m4_t ATESTCTL1
Internal.
Definition:
cc26xx_cc13xx_adi.h:52
adi_3_refsys_regs_m4_t::DCDCCTL0
reg8_m4_t DCDCCTL0
DCDC Control 0.
Definition:
cc26xx_cc13xx_adi.h:57
adi_3_refsys_regs_t
ADI_3_REFSYS registers.
Definition:
cc26xx_cc13xx_adi.h:27
adi_3_refsys_regs_t::DCDCCTL5
reg8_t DCDCCTL5
Internal.
Definition:
cc26xx_cc13xx_adi.h:39
adi_3_refsys_regs_t::DCDCCTL0
reg8_t DCDCCTL0
DCDC Control 0.
Definition:
cc26xx_cc13xx_adi.h:34
adi_3_refsys_regs_t::DCDCCTL1
reg8_t DCDCCTL1
DCDC Control 1.
Definition:
cc26xx_cc13xx_adi.h:35
adi_3_refsys_regs_t::REFSYSCTL3
reg8_t REFSYSCTL3
Internal.
Definition:
cc26xx_cc13xx_adi.h:33
adi_3_refsys_regs_t::ATESTCTL1
reg8_t ATESTCTL1
Internal.
Definition:
cc26xx_cc13xx_adi.h:29
adi_3_refsys_regs_t::__reserved1
reg8_t __reserved1
Reserved.
Definition:
cc26xx_cc13xx_adi.h:28
adi_3_refsys_regs_t::DCDCCTL4
reg8_t DCDCCTL4
Internal.
Definition:
cc26xx_cc13xx_adi.h:38
adi_3_refsys_regs_t::REFSYSCTL0
reg8_t REFSYSCTL0
Internal.
Definition:
cc26xx_cc13xx_adi.h:30
adi_3_refsys_regs_t::DCDCCTL3
reg8_t DCDCCTL3
Internal.
Definition:
cc26xx_cc13xx_adi.h:37
adi_3_refsys_regs_t::REFSYSCTL2
reg8_t REFSYSCTL2
Internal.
Definition:
cc26xx_cc13xx_adi.h:32
adi_3_refsys_regs_t::DCDCCTL2
reg8_t DCDCCTL2
DCDC Control 2.
Definition:
cc26xx_cc13xx_adi.h:36
adi_3_refsys_regs_t::REFSYSCTL1
reg8_t REFSYSCTL1
Internal.
Definition:
cc26xx_cc13xx_adi.h:31
reg8_m4_t
Masked 8-bit register.
Definition:
cc26xx_cc13xx.h:41
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