Timing configuration for SDRAM. More...

Detailed Description

Timing configuration for SDRAM.

Definition at line 207 of file cpu_fmc.h.

#include <cpu_fmc.h>

Data Fields
uint8_t	row_to_col_delay
	Row to column delay in SDCLK clock cycles [1..16], delay between Activate and Read/Write command.

uint8_t	row_precharge
	Row precharge delay in SDCLK clock cycles [1..15], delay between Precharge and another command.

uint8_t	recovery_delay
	Recovery delay in SDCLK clock cycles [1..15], delay between Write and Precharge command.

uint8_t	row_cylce
	Row cycle delay in SDCLK clock cycles [1..15], delay between Refresh and Activate command.

uint8_t	self_refresh
	Self refresh time in SDCLK clock cycles [1..15].

uint8_t	exit_self_refresh
	Exit self-refresh delay in SDCLK clock cycles [1..15], delay between Self-Refresh and Activate command.

uint8_t	load_mode_register
	Load Mode Register to Activate delay in SDCLK clock cycles [1..15], delay between Load Mode Register and Activate command.

uint8_t	refresh_period
	Refresh period in milliseconds.

The documentation for this struct was generated from the following file:

Data Fields