cpu_fmc.h

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/*
 * SPDX-FileCopyrightText: 2023 Gunar Schorcht
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include <stdint.h>
 
#include "cpu.h"
#include "periph/cpu_gpio.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifndef FMC_BANK_CONFIG
#define FMC_BANK_CONFIG(n)  (&fmc_bank_config[n])
#endif
 
#if MODULE_PERIPH_FMC_32BIT || DOXYGEN
#define FMC_DATA_PIN_NUMOF      (32)
#elif MODULE_PERIPH_FMC_16BIT
#define FMC_DATA_PIN_NUMOF      (16)
#else
#define FMC_DATA_PIN_NUMOF      (8)
#endif
 
#if MODULE_PERIPH_FMC_NOR_SRAM || DOXYGEN
#define FMC_ADDR_PIN_NUMOF      (26)
#elif MODULE_PERIPH_FMC_SDRAM
#define FMC_ADDR_PIN_NUMOF      (13)
#else
#define FMC_ADDR_PIN_NUMOF      (0)
#endif
 
#if DOXYGEN
#define FMC_RAM_ADDR    0x60000000
 
#define FMC_RAM_LEN     1024K
#endif
 
typedef enum {
    FMC_MODE_A = 0,             
    FMC_MODE_B = 1,             
    FMC_MODE_C = 2,             
    FMC_MODE_D = 3,             
} fmc_access_mode_t;
 
typedef struct {
    fmc_access_mode_t mode;     
    uint8_t clk_div;            
    uint8_t addr_setup;         
    uint8_t addr_hold;          
    uint8_t data_setup;         
    uint8_t data_latency;       
    uint8_t bus_turnaround;     
} fmc_nor_sram_timing_t;
 
typedef struct {
    uint8_t sub_bank;               
    bool mux_enable;                
    bool wait_enable;               
    bool ext_mode;                  
    fmc_nor_sram_timing_t r_timing; 
    fmc_nor_sram_timing_t w_timing; 
} fmc_nor_sram_bank_conf_t;
typedef enum {
    FMC_BURST_LENGTH_1 = 0,     /* Burst length is 1 */
    FMC_BURST_LENGTH_2 = 1,     /* Burst length is 2 */
    FMC_BURST_LENGTH_4 = 2,     /* Burst length is 4 */
    FMC_BURST_LENGTH_8 = 3,     /* Burst length is 8 */
    FMC_BURST_LENGTH_16 = 4,    /* Burst length is 16 */
    FMC_BURST_LENGTH_32 = 5,    /* Burst length is 32 */
    FMC_BURST_LENGTH_64 = 6,    /* Burst length is 64 */
    FMC_BURST_LENGTH_FULL = 7,  /* Burst length is full page */
} fmc_bust_length_t;
 
typedef struct {
    uint8_t row_to_col_delay;   
    uint8_t row_precharge;      
    uint8_t recovery_delay;     
    uint8_t row_cylce;          
    uint8_t self_refresh;       
    uint8_t exit_self_refresh;  
    uint8_t load_mode_register; 
    uint8_t refresh_period;     
} fmc_sdram_timing_t;
 
typedef struct {
    uint8_t clk_period;          
    uint8_t row_bits;            
    uint8_t col_bits;            
    uint8_t cas_latency;         
    uint8_t read_delay;          
    bool four_banks;             
    bool write_protect;          
    bool burst_read;             
    bool burst_write;            
    bool burst_interleaved;      
    fmc_bust_length_t burst_len; 
    fmc_sdram_timing_t timing;   
} fmc_sdram_bank_conf_t;
typedef struct {
    gpio_t pin;                 
    gpio_af_t af;               
} fmc_gpio_t;
 
typedef struct {
    uint8_t bus;                         
    uint32_t rcc_mask;                   
    fmc_gpio_t data[FMC_DATA_PIN_NUMOF]; 
#if FMC_ADDR_PIN_NUMOF || DOXYGEN
    fmc_gpio_t addr[FMC_ADDR_PIN_NUMOF]; 
#endif
    /* signals used by all kind of memories */
    fmc_gpio_t nbl0_pin;                 
    fmc_gpio_t nbl1_pin;                 
    fmc_gpio_t nbl2_pin;                 
    fmc_gpio_t nbl3_pin;                 
    fmc_gpio_t nwait_pin;                
#if MODULE_PERIPH_FMC_NOR_SRAM
    /* NORs, PSRAMs, and SRAMs use CLK, NOE, NWE, NE, and NADV signals **/
    fmc_gpio_t clk_pin;                  
    fmc_gpio_t noe_pin;                  
    fmc_gpio_t nwe_pin;                  
    fmc_gpio_t ne1_pin;                  
    fmc_gpio_t ne2_pin;                  
    fmc_gpio_t ne3_pin;                  
    fmc_gpio_t ne4_pin;                  
    fmc_gpio_t nadv_pin;                 
#endif /* MODULE_PERIPH_FMC_NORSRAM */
#if MODULE_PERIPH_FMC_SDRAM
    /* SDRAMs use BAx, CLK, RAS, CAS, WE, ... signals **/
    fmc_gpio_t ba0_pin;                  
    fmc_gpio_t ba1_pin;                  
    fmc_gpio_t sdclk_pin;                
    fmc_gpio_t sdnwe_pin;                
    fmc_gpio_t sdnras_pin;               
    fmc_gpio_t sdncas_pin;               
    fmc_gpio_t sdcke0_pin;               
    fmc_gpio_t sdcke1_pin;               
    fmc_gpio_t sdne0_pin;                
    fmc_gpio_t sdne1_pin;                
#endif /* MODULE_PERIPH_FMC_SDRAM */
} fmc_conf_t;
 
typedef enum {
    FMC_BANK_1 = 1,             
#if defined(FMC_Bank2_3_R_BASE)
    FMC_BANK_2 = 2,             
#endif
#if defined(FMC_Bank2_3_R_BASE) || defined(FMC_Bank3_R_BASE)
    FMC_BANK_3 = 3,             
#endif
#if defined(FMC_Bank4_R_BASE)
    FMC_BANK_4 = 4,             
#endif
#if defined(FMC_Bank5_6_R_BASE)
    FMC_BANK_5 = 5,             
    FMC_BANK_6 = 6,             
#endif
} fmc_bank_t;
 
typedef enum {
    FMC_SRAM = 0,               
    FMC_PSRAM = 1,              
    FMC_NOR = 2,                
    FMC_NAND = 3,               
    FMC_SDRAM = 4,              
} fmc_mem_type_t;
 
typedef enum {
    FMC_BUS_WIDTH_8BIT = 0,     
    FMC_BUS_WIDTH_16BIT = 1,    
    FMC_BUS_WIDTH_32BIT = 2,    
} fmc_bus_width_t;
 
typedef struct {
    fmc_bank_t bank;                
    fmc_mem_type_t mem_type;        
    fmc_bus_width_t data_width;     
    uint32_t address;               
    uint32_t size;                  
    union {
        fmc_nor_sram_bank_conf_t nor_sram;  /* Configuration in case of NOR/PSRAM/SRAM */
        fmc_sdram_bank_conf_t sdram;        /* Configuration in case of SDRAM */
    };
} fmc_bank_conf_t;
 
typedef uint8_t fmc_bank_id_t;  
#ifdef __cplusplus
}
#endif