Bank configuration structure for SDRAM. More...

Detailed Description

Bank configuration structure for SDRAM.

Definition at line 234 of file cpu_fmc.h.

#include <cpu_fmc.h>

Data Fields
uint8_t	clk_period
	CLK period [0,2,3] (0 - disabled, n * HCLK cycles)

uint8_t	row_bits
	Number row address bits [11..13].

uint8_t	col_bits
	Number column address bits [8..11].

uint8_t	cas_latency
	CAS latency in SDCLK clock cycles [1..3].

uint8_t	read_delay
	Delay for reading data after CAS latency in HCLKs [0..2].

bool	four_banks
	SDRAM has four internal banks.

bool	write_protect
	Write protection enabled.

bool	burst_read
	Burst read mode enabled.

bool	burst_write
	Burst write mode enabled.

bool	burst_interleaved
	Burst mode interleaved, otherwise sequential.

fmc_bust_length_t	burst_len
	Burst length as an exponent of a power of two.

fmc_sdram_timing_t	timing
	SDRAM Timing configuration.

The documentation for this struct was generated from the following file:

Data Fields