periph_conf.h
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1 /*
2  * Copyright (C) 2018 Inria
3  * 2023 Gunar Schorcht
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 /* Add specific clock configuration (HSE, LSE) for this board here */
25 #ifndef CONFIG_BOARD_HAS_LSE
26 #define CONFIG_BOARD_HAS_LSE 1
27 #endif
28 
29 #include "periph_cpu.h"
30 #include "clk_conf.h"
31 #include "cfg_rtt_default.h"
32 #include "cfg_usb_otg_fs.h"
33 #include "lcd_fmc.h"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
43 static const dma_conf_t dma_config[] = {
44  { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX */
45  { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
46  { .stream = 3 }, /* DMA1 Channel 4 - SPI2_RX / USART1_TX */
47  { .stream = 4 }, /* DMA1 Channel 5 - SPI2_TX */
48  { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
49  { .stream = 13 }, /* DMA2 Channel 6 - LPUART1_TX */
50  { .stream = 11 }, /* DMA2 Channel 4 - SDMMC1 */
51 };
52 
53 #define DMA_0_ISR isr_dma1_channel2
54 #define DMA_1_ISR isr_dma1_channel3
55 #define DMA_2_ISR isr_dma1_channel4
56 #define DMA_3_ISR isr_dma1_channel5
57 #define DMA_4_ISR isr_dma1_channel7
58 #define DMA_5_ISR isr_dma2_channel6
59 #define DMA_6_ISR isr_dma2_channel4
60 
61 #define DMA_NUMOF ARRAY_SIZE(dma_config)
100 static const adc_conf_t adc_config[] = {
101  { .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 13 }, /* A0, ADC12_IN13 */
102  { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* A1, ADC123_IN2 */
103  { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 4 }, /* A2, ADC123_IN4 */
104  { .pin = GPIO_PIN(PORT_F, 10), .dev = 2, .chan = 13 }, /* A3, ADC3_IN13 */
105  { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 6 }, /* A4, ADC12_IN6, SB26 closed */
106  { .pin = GPIO_PIN(PORT_C, 0), .dev = 1, .chan = 13 }, /* A5, ADC12_IN13, SB28 closed */
107  { .pin = GPIO_UNDEF, .dev = 0, .chan = 0 }, /* V_REFINT, ADC1_IN0 */
108  { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* V_BAT, ADC1_IN18 */
109 #if !MODULE_PERIPH_DAC
110  { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 9 }, /* STMOD+_ADC, ADC12_IN9 */
111 #else
112  { .pin = GPIO_UNDEF, .dev = 1, .chan = 17 }, /* DAC1, ADC2_IN17 */
113 #endif
114 };
115 
119 #define ADC_NUMOF ARRAY_SIZE(adc_config)
120 
124 #define VBAT_ADC ADC_LINE(7)
125 
129 #define VREFINT_ADC ADC_LINE(6)
130 
139 #ifndef VREFBUF_ENABLE
140 #define VREFBUF_ENABLE (1)
141 #endif
142 
154 static const dac_conf_t dac_config[] = {
155  { GPIO_PIN(PORT_A, 4), .chan = 0 }, /* STMod+_ADC pin */
156 #if !MODULE_PERIPH_SPI
157  { GPIO_PIN(PORT_A, 5), .chan = 1 }, /* Arduino D13, conflicts with SPI_DEV(0) */
158 #endif
159 };
160 
164 #define DAC_NUMOF ARRAY_SIZE(dac_config)
175 static const fmc_conf_t fmc_config = {
176  .bus = AHB3,
177  .rcc_mask = RCC_AHB3ENR_FMCEN,
178 #if MODULE_PERIPH_FMC_NOR_SRAM
179  .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 1 */
180  .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* PSRAM_NE signal, subbank 2 */
181  .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* PSRAM/LCD_OE signal (OE) */
182  .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* PSRAM/LCD_WE signal (WE) */
183  .addr = {
184  { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 signal */
185  { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
186  { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
187  { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
188  { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
189  { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
190  { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
191  { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
192  { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
193  { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
194  { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
195  { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
196  { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
197  { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
198  { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
199  { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
200  { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
201  { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
202  { .pin = GPIO_PIN(PORT_D, 13), .af = GPIO_AF12, }, /* PSRAM_A18 / LCD_RS signal */
203  },
204 #endif
205  .data = {
206  { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* PSRAM_D0 / LCD_D0 signal */
207  { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* PSRAM_D1 / LCD_D1 signal */
208  { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* PSRAM_D2 / LCD_D2 signal */
209  { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* PSRAM_D3 / LCD_D3 signal */
210  { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* PSRAM_D4 / LCD_D4 signal */
211  { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* PSRAM_D5 / LCD_D5 signal */
212  { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* PSRAM_D6 / LCD_D6 signal */
213  { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* PSRAM_D7 / LCD_D7 signal */
214 #if MODULE_PERIPH_FMC_16BIT
215  { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* PSRAM_D8 / LCD_D8 signal */
216  { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* PSRAM_D9 / LCD_D9 signal */
217  { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* PSRAM_D10 / LCD_D10 signal */
218  { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* PSRAM_D11 / LCD_D11 signal */
219  { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* PSRAM_D12 / LCD_D12 signal */
220  { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* PSRAM_D13 / LCD_D13 signal */
221  { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* PSRAM_D14 / LCD_D14 signal */
222  { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* PSRAM_D15 / LCD_D15 signal */
223 #endif
224  },
225  .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
226  .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
227 };
228 
240  /* bank 1, subbank 2 is used for PSRAM with asynchronuous
241  * access in Mode 1, i.e. write timings are not used */
242  {
243  .bank = FMC_BANK_1,
244  .mem_type = FMC_SRAM,
245  .data_width = FMC_BUS_WIDTH_16BIT,
246  .address = 0x64000000, /* Bank 1, subbank 2 is mapped to 0x64000000 */
247  .size = MiB(1), /* Size in Mbyte, 512K x 16 bit */
248  .nor_sram = {
249  .sub_bank = 2,
250  .ext_mode = false, /* Mode 1 used, no separate w_timing */
251  /* timings for IS66WV51216EBLL-70BLI */
252  .r_timing = { .addr_setup = 6, /* t_AA = 70 ns (6 HCLKs a 12.5 ns) */
253  .data_setup = 2, /* t_SD = 30 ns (3 HCLKs a 12.5 ns) */
254  .bus_turnaround = 1, }, /* 1 HCLK a 12.5 ns */
255  },
256  },
257  /* bank 1, subbank 1 is used for LCD with asynchronuous
258  * access in Mode 1, i.e. write timings are not used */
259  {
260  .bank = FMC_BANK_1,
261  .mem_type = FMC_SRAM,
262  .data_width = FMC_BUS_WIDTH_16BIT,
263  .address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
264  .size = 2, /* 1 word for command @ 0x60000000 and
265  1 word for data @ 0x60080000 */
266  .nor_sram = {
267  .sub_bank = 1,
268  .ext_mode = false, /* Mode 1 used, no separate w_timing */
269  /* timing requirements for ST7789H2:
270  - t_AST min 0 ns (Address setup time)
271  - t_DST min 10 ns (Data setup time)
272  - t_WRL min 15 ns (WE LOW time)
273  - t_WRH min 15 ns (WE HIGH time)
274  - t_WRC min 66 ns (WE cycle time) */
275  .r_timing = { .addr_setup = 1, /* t_AST = 12 ns (1 HCLKs a 12.5 ns) */
276  .data_setup = 3, /* t_DST = 37 ns (3 HCLKs a 12.5 ns) */
277  .bus_turnaround = 2, }, /* t_WRH = 25 ns (2 HCLKs a 12.5 ns) */
278  },
279  },
280 };
281 
285 #define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
286 
290 static const lcd_fmc_desc_t lcd_fmc_desc[] = {
291  {
292  .bank = FMC_BANK_CONFIG(1), /* second bank (fmc_bank_config[1]) is used */
293  .cmd_offset = 0x0, /* address 0x60000000 (offset 0x00000) used for commands */
294  .data_offset = 0x80000, /* address 0x60080000 (offset 0x80000) used for data */
295  }
296 };
297 
304 #define LCD_FMC_NUMOF 1
305 
315 static const i2c_conf_t i2c_config[] = {
316  { /* Shared between Arduino D14/D15 and STMod+ connector */
317  .dev = I2C1,
318  .speed = I2C_SPEED_NORMAL,
319  .scl_pin = GPIO_PIN(PORT_B, 8),
320  .sda_pin = GPIO_PIN(PORT_B, 7),
321  .scl_af = GPIO_AF4,
322  .sda_af = GPIO_AF4,
323  .bus = APB1,
324  .rcc_mask = RCC_APB1ENR1_I2C1EN,
325  .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
326  .irqn = I2C1_ER_IRQn,
327  },
328  { /* Multi Function eXpander (MFX_x) I2C Address 0x42,
329  * Stereo Codec Cirrus Logic CS42L51-CNZ (CODEC_x), I2C Address 0x4a (AD0 = 0)
330  * Capacitive Touch Panel (CTP_x) FT6206, I2C Address 0x38
331  * Digital Camera Module (DCMI_x),
332  */
333  .dev = I2C2,
334  .speed = I2C_SPEED_NORMAL,
335  .scl_pin = GPIO_PIN(PORT_H, 4),
336  .sda_pin = GPIO_PIN(PORT_B, 14),
337  .scl_af = GPIO_AF4,
338  .sda_af = GPIO_AF4,
339  .bus = APB1,
340  .rcc_mask = RCC_APB1ENR1_I2C2EN,
341  .rcc_sw_mask = RCC_CCIPR_I2C2SEL_1, /* HSI (16 MHz) */
342  .irqn = I2C2_ER_IRQn,
343  },
344 };
345 
346 #define I2C_0_ISR isr_i2c1_er
347 #define I2C_1_ISR isr_i2c2_er
348 
349 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
364 static const pwm_conf_t pwm_config[] = {
365  {
366  .dev = TIM8,
367  .rcc_mask = RCC_APB2ENR_TIM8EN,
368  .chan = { { .pin = GPIO_PIN(PORT_H, 15), .cc_chan = 6}, /* D3, TIM8_CH3N */
369  { .pin = GPIO_PIN(PORT_I, 6), .cc_chan = 1}, /* D6, TIM8_CH2 */
370  { .pin = GPIO_PIN(PORT_H, 13), .cc_chan = 4}, /* D9, TIM8_CH1N */
371  { .pin = GPIO_UNDEF, .cc_chan = 0} },
372  .af = GPIO_AF3,
373  .bus = APB2
374  },
375  {
376  .dev = TIM4,
377  .rcc_mask = RCC_APB1ENR1_TIM4EN,
378  .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 3}, /* D5, TIM4_CH4 */
379  { .pin = GPIO_UNDEF, .cc_chan = 0},
380  { .pin = GPIO_UNDEF, .cc_chan = 0},
381  { .pin = GPIO_UNDEF, .cc_chan = 0} },
382  .af = GPIO_AF2,
383  .bus = APB1
384  },
385  {
386  .dev = TIM5,
387  .rcc_mask = RCC_APB1ENR1_TIM5EN,
388  .chan = { { .pin = GPIO_PIN(PORT_A, 0), .cc_chan = 0}, /* STMOD+_PWM, TIM5_CH1 */
389  { .pin = GPIO_UNDEF, .cc_chan = 0},
390  { .pin = GPIO_UNDEF, .cc_chan = 0},
391  { .pin = GPIO_UNDEF, .cc_chan = 0} },
392  .af = GPIO_AF2,
393  .bus = APB1
394  },
395 };
396 
397 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
408 static const sdmmc_conf_t sdmmc_config[] = {
409  {
410  .dev = SDMMC1,
411  .bus = APB2,
412  .rcc_mask = RCC_APB2ENR_SDMMC1EN,
413  .cd = GPIO_UNDEF, /* CD is connected to MFX GPIO8 */
414  .clk = { GPIO_PIN(PORT_C, 12), GPIO_AF12 },
415  .cmd = { GPIO_PIN(PORT_D, 2), GPIO_AF12 },
416  .dat0 = { GPIO_PIN(PORT_C, 8), GPIO_AF12 },
417  .dat1 = { GPIO_PIN(PORT_C, 9), GPIO_AF12 },
418  .dat2 = { GPIO_PIN(PORT_C, 10), GPIO_AF12 },
419  .dat3 = { GPIO_PIN(PORT_C, 11), GPIO_AF12 },
420 #if MODULE_PERIPH_DMA
421  .dma = 6,
422  .dma_chan = 7,
423 #endif
424  .irqn = SDMMC1_IRQn
425  },
426 };
427 
431 #define SDMMC_CONFIG_NUMOF 1
432 
447 static const spi_conf_t spi_config[] = {
448  { /* Arduino connector */
449  .dev = SPI1,
450  .mosi_pin = GPIO_PIN(PORT_B, 5),
451  .miso_pin = GPIO_PIN(PORT_B, 4),
452  .sclk_pin = GPIO_PIN(PORT_A, 5),
453  .cs_pin = GPIO_PIN(PORT_A, 15),
454  .mosi_af = GPIO_AF5,
455  .miso_af = GPIO_AF5,
456  .sclk_af = GPIO_AF5,
457  .cs_af = GPIO_AF5,
458  .rccmask = RCC_APB2ENR_SPI1EN,
459  .apbbus = APB2,
460 #if MODULE_PERIPH_DMA
461  .rx_dma = 0, /* DMA1 Channel 2 */
462  .rx_dma_chan = 1, /* CxS = 1 */
463  .tx_dma = 1, /* DMA1 Channel 3 */
464  .tx_dma_chan = 1, /* CxS = 1 */
465 #endif
466  },
467 #if MODULE_PERIPH_SPI_STMOD
468  { /* Pmod/STMod+ connector if solder bridges SB4, SB5, SB9 are closed */
469  .dev = SPI2,
470  .mosi_pin = GPIO_PIN(PORT_B, 15),
471  .miso_pin = GPIO_PIN(PORT_I, 2),
472  .sclk_pin = GPIO_PIN(PORT_I, 1),
473  .cs_pin = GPIO_PIN(PORT_G, 1),
474  .mosi_af = GPIO_AF5,
475  .miso_af = GPIO_AF5,
476  .sclk_af = GPIO_AF5,
477  .cs_af = GPIO_AF5,
478  .rccmask = RCC_APB1ENR1_SPI2EN,
479  .apbbus = APB1,
480 #if MODULE_PERIPH_DMA
481  .rx_dma = 2, /* DMA1 Channel 4 */
482  .rx_dma_chan = 1, /* CxS = 1 */
483  .tx_dma = 3, /* DMA1 Channel 5 */
484  .tx_dma_chan = 1, /* CxS = 1 */
485 #endif
486  },
487 #endif
488 };
489 
490 #define SPI_NUMOF ARRAY_SIZE(spi_config)
497 static const timer_conf_t timer_config[] = {
498  {
499  .dev = TIM2,
500  .max = 0xffffffff,
501  .rcc_mask = RCC_APB1ENR1_TIM2EN,
502  .bus = APB1,
503  .irqn = TIM2_IRQn
504  },
505  {
506  .dev = TIM3,
507  .max = 0xffffffff,
508  .rcc_mask = RCC_APB1ENR1_TIM3EN,
509  .bus = APB1,
510  .irqn = TIM3_IRQn
511  },
512 };
513 
514 #define TIMER_0_ISR isr_tim2
515 #define TIMER_1_ISR isr_tim3
516 
517 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
531 static const uart_conf_t uart_config[] = {
532  { /* Virtual COM Port / ST-Link */
533  .dev = USART2,
534  .rcc_mask = RCC_APB1ENR1_USART2EN,
535  .rx_pin = GPIO_PIN(PORT_D, 6),
536  .tx_pin = GPIO_PIN(PORT_A, 2),
537  .rx_af = GPIO_AF7,
538  .tx_af = GPIO_AF7,
539  .bus = APB1,
540  .irqn = USART2_IRQn,
541 #if MODULE_PERIPH_UART_HW_FC
542  .cts_pin = GPIO_UNDEF, /* CTS is not connected */
543  .rts_pin = GPIO_UNDEF, /* RTS is not connected */
544 #endif
545  .type = STM32_USART,
546  .clk_src = 0, /* Use APB clock */
547 #if MODULE_PERIPH_DMA
548  .dma = 4, /* DMA1 Channel 7 */
549  .dma_chan = 2, /* CxS = 2 */
550 #endif
551  },
552  { /* Arduino connector RX/TX (D0/D1) */
553  .dev = LPUART1,
554  .rcc_mask = RCC_APB1ENR2_LPUART1EN,
555  .rx_pin = GPIO_PIN(PORT_G, 8),
556  .tx_pin = GPIO_PIN(PORT_G, 7),
557  .rx_af = GPIO_AF8,
558  .tx_af = GPIO_AF8,
559  .bus = APB12,
560  .irqn = LPUART1_IRQn,
561 #if MODULE_PERIPH_UART_HW_FC
562  .cts_pin = GPIO_UNDEF, /* CTS is not connected */
563  .rts_pin = GPIO_UNDEF, /* RTS is not connected */
564 #endif
565  .type = STM32_LPUART,
566  .clk_src = 0, /* Use APB clock */
567 #if MODULE_PERIPH_DMA
568  .dma = 5, /* DMA2 Channel 6 */
569  .dma_chan = 4, /* CxS = 4 */
570 #endif
571  },
572 
573 #if !MODULE_PERIPH_SPI_STMOD
574  { /* Pmod/STMod+ connector if solder bridges SB6, SB7, SB8 are closed (default) */
575  .dev = USART1,
576  .rcc_mask = RCC_APB2ENR_USART1EN,
577  .rx_pin = GPIO_PIN(PORT_G, 10),
578  .tx_pin = GPIO_PIN(PORT_B, 6),
579  .rx_af = GPIO_AF7,
580  .tx_af = GPIO_AF7,
581  .bus = APB2,
582  .irqn = USART1_IRQn,
583 #if MODULE_PERIPH_UART_HW_FC
584  .cts_pin = GPIO_PIN(PORT_G, 11),
585  .rts_pin = GPIO_PIN(PORT_G, 12),
586  .cts_af = GPIO_AF7,
587  .rts_af = GPIO_AF7,
588 #endif
589  .type = STM32_USART,
590  .clk_src = 0, /* Use APB clock */
591 #if MODULE_PERIPH_DMA
592  .dma = 2, /* DMA1 Channel 4 */
593  .dma_chan = 2, /* CxS = 2 */
594 #endif
595  },
596 #endif /* !MODULE_PERIPH_SPI_STMOD */
597 };
598 
599 #define UART_0_ISR (isr_usart2)
600 #define UART_1_ISR (isr_lpuart1)
601 #define UART_2_ISR (isr_usart1)
602 
603 #define UART_NUMOF ARRAY_SIZE(uart_config)
606 #ifdef __cplusplus
607 }
608 #endif
609 
610 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_G
port G
Definition: periph_cpu.h:53
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_F
port F
Definition: periph_cpu.h:52
@ PORT_E
port E
Definition: periph_cpu.h:51
@ PORT_A
port A
Definition: periph_cpu.h:47
@ PORT_D
port D
Definition: periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
@ PORT_H
port H
Definition: periph_cpu.h:52
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:40
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
static const dac_conf_t dac_config[]
DAC configuration.
Definition: periph_conf.h:253
static const sdmmc_conf_t sdmmc_config[]
SDIO/SDMMC static configuration struct.
Definition: periph_conf.h:408
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Definition: periph_conf.h:290
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
Definition: periph_conf.h:239
static const fmc_conf_t fmc_config
FMC controller configuration.
Definition: periph_conf.h:175
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:111
@ GPIO_AF3
use alternate function 3
Definition: cpu_gpio.h:105
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:115
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: cpu_uart.h:39
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:38
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
Definition: cpu_fmc.h:75
@ FMC_SRAM
SRAM.
Definition: cpu_fmc.h:341
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition: cpu_fmc.h:353
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
Definition: cpu_fmc.h:321
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
ADC device configuration.
Definition: periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:288
DAC line configuration data.
Definition: periph_cpu.h:301
DMA configuration.
Definition: cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:55
Bank configuration structure.
Definition: cpu_fmc.h:360
fmc_bank_t bank
Bank1 .
Definition: cpu_fmc.h:361
FMC peripheral configuration.
Definition: cpu_fmc.h:278
uint8_t bus
AHB/APB bus.
Definition: cpu_fmc.h:279
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
Descriptor of the FMC bank used for a LCD.
Definition: lcd_fmc.h:49
const fmc_bank_conf_t * bank
FMC bank config used for the LCD.
Definition: lcd_fmc.h:50
PWM device configuration.
mini_timer_t * dev
Timer used.
SDMMC slot configuration.
Definition: periph_cpu.h:704
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
Timer device configuration.
Definition: periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:265
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219
#define MiB(x)
A macro to return the bytes in x MiB.
Definition: units.h:34