periph_cpu_common.h

Go to the documentation of this file.

/*
 * Copyright (C) 2015-2018 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_COMMON_H
#define PERIPH_CPU_COMMON_H
 
#include "cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifdef NRF_FICR_S
#define NRF_FICR NRF_FICR_S
#endif
 
#ifdef CPU_MODEL_NRF52832XXAA
#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
#endif
 
#define PROVIDES_PM_OFF
#ifdef FICR_INFO_DEVICEID_DEVICEID_Msk
#define CPUID_ADDR          (&NRF_FICR->INFO.DEVICEID[0])
#else
#define CPUID_ADDR          (&NRF_FICR->DEVICEID[0])
#endif
#define CPUID_LEN           (8U)
 
#if GPIO_COUNT > 1
#define GPIO_PIN(x, y)      ((x << 5) | y)
#else
#define GPIO_PIN(x, y)      ((x & 0) | y)
#endif
 
/* The precise value matters where GPIO_UNDEF is set in registers like
 * PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
#define GPIO_UNDEF          (UINT8_MAX)
 
#ifdef NRF_GPIOTE0_S
#define ISR_GPIOTE isr_gpiote0
#else
#define ISR_GPIOTE isr_gpiote
#endif
 
#define GPIO_MODE(oe, ic, pr, dr)   (oe | (ic << 1) | (pr << 2) | (dr << 8))
 
#ifndef DOXYGEN /* BEGIN: GPIO LL overwrites */
#define HAVE_GPIO_SLEW_T
typedef enum {
    GPIO_SLEW_SLOWEST = 0,
    GPIO_SLEW_SLOW = 0,
    GPIO_SLEW_FAST = 0,
    GPIO_SLEW_FASTEST = 0,
} gpio_slew_t;
 
#define HAVE_GPIO_PULL_STRENGTH_T
typedef enum {
    GPIO_PULL_WEAKEST = 0,
    GPIO_PULL_WEAK = 0,
    GPIO_PULL_STRONG = 0,
    GPIO_PULL_STRONGEST = 0
} gpio_pull_strength_t;
 
#define HAVE_GPIO_DRIVE_STRENGTH_T
typedef enum {
    GPIO_DRIVE_WEAKEST = 0,
    GPIO_DRIVE_WEAK = 0,
    GPIO_DRIVE_STRONG = 1,
    GPIO_DRIVE_STRONGEST = 1
} gpio_drive_strength_t;
 
#define HAVE_GPIO_IRQ_TRIG_T
typedef enum {
    GPIO_TRIGGER_EDGE_RISING    = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos,
    GPIO_TRIGGER_EDGE_FALLING   = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos,
    GPIO_TRIGGER_EDGE_BOTH      = GPIO_TRIGGER_EDGE_RISING | GPIO_TRIGGER_EDGE_FALLING,
    GPIO_TRIGGER_LEVEL_HIGH     = 0, 
    GPIO_TRIGGER_LEVEL_LOW      = 0, 
} gpio_irq_trig_t;
 
#define HAVE_GPIO_PULL_T
typedef enum {
    GPIO_FLOATING = 0,
    GPIO_PULL_UP = GPIO_PIN_CNF_PULL_Pullup,
    GPIO_PULL_DOWN = GPIO_PIN_CNF_PULL_Pulldown,
    GPIO_PULL_KEEP = 2,
} gpio_pull_t;
 
#define HAVE_GPIO_STATE_T
typedef enum {
    GPIO_OUTPUT_PUSH_PULL,
    GPIO_OUTPUT_OPEN_DRAIN,
    GPIO_OUTPUT_OPEN_SOURCE,
    GPIO_INPUT,
    GPIO_USED_BY_PERIPHERAL,
    GPIO_DISCONNECT,
} gpio_state_t;
 
#define HAVE_GPIO_CONF_T
typedef union gpio_conf_nrf5x gpio_conf_t;
 
#endif
 
union gpio_conf_nrf5x {
    uint8_t bits;  
    struct {
        gpio_state_t state                      : 3;
        gpio_pull_t pull                        : 2;
        gpio_drive_strength_t drive_strength    : 1;
        bool initial_value                      : 1;
        uint8_t                                 : 1; /*< padding */
    };
};
/* END: GPIO LL overwrites */
 
#if !defined(DOXYGEN) && (defined(CPU_NRF53) || defined(CPU_NRF9160))
#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
 
#define SPI_FREQUENCY_FREQUENCY_K125 SPIM_FREQUENCY_FREQUENCY_K125
#define SPI_FREQUENCY_FREQUENCY_K500 SPIM_FREQUENCY_FREQUENCY_K500
#define SPI_FREQUENCY_FREQUENCY_M1 SPIM_FREQUENCY_FREQUENCY_M1
#define SPI_FREQUENCY_FREQUENCY_M4 SPIM_FREQUENCY_FREQUENCY_M4
#define SPI_FREQUENCY_FREQUENCY_M8 SPIM_FREQUENCY_FREQUENCY_M8
#define SPI_CONFIG_CPHA_Msk SPIM_CONFIG_CPHA_Msk
#define SPI_CONFIG_CPOL_Msk SPIM_CONFIG_CPOL_Msk
#endif
 
#define SPI_HWCS(x)         (SPI_CS_UNDEF)
 
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
#ifndef DOXYGEN
#define HAVE_GPIO_T
typedef uint8_t gpio_t;
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN       = GPIO_MODE(0, 0, 0, 0), 
    GPIO_IN_PD    = GPIO_MODE(0, 0, 1, 0), 
    GPIO_IN_PU    = GPIO_MODE(0, 0, 3, 0), 
    GPIO_IN_OD_PU = GPIO_MODE(0, 0, 3, 6), 
    GPIO_OUT      = GPIO_MODE(1, 1, 0, 0), 
    GPIO_OD       = (0xff),                
    GPIO_OD_PU    = (0xfe)                 
} gpio_mode_t;
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_FALLING = 2,       
    GPIO_RISING  = 1,       
    GPIO_BOTH    = 3        
} gpio_flank_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    NRF_TIMER_Type *dev;    
    uint8_t channels;
    uint8_t bitmode;        
    uint8_t irqn;           
} timer_conf_t;
 
#define PERIPH_TIMER_PROVIDES_SET   1
 
#define TIMER_CHANNEL_NUMOF 5
 
#ifndef DOXYGEN
#define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0 = 0,                                             
    SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,                           
    SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,                           
    SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)    
} spi_mode_t;
#define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,  
    SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,  
    SPI_CLK_1MHZ   = SPI_FREQUENCY_FREQUENCY_M1,    
    SPI_CLK_5MHZ   = SPI_FREQUENCY_FREQUENCY_M4,    
    SPI_CLK_10MHZ  = SPI_FREQUENCY_FREQUENCY_M8     
} spi_clk_t;
#endif /* ndef DOXYGEN */
 
#define NWDT_TIME_LOWER_LIMIT          (1)
/* Set upper limit to the maximum possible value that could go in CRV register */
#define NWDT_TIME_UPPER_LIMIT          ((UINT32_MAX >> 15) * US_PER_MS + 1)
typedef struct {
    gpio_t a_pin;          
    gpio_t b_pin;          
    gpio_t led_pin;        
    uint8_t sample_period; 
    bool debounce_filter;  
} qdec_conf_t;
 
uint8_t gpio_int_get_exti(gpio_t pin);
 
typedef struct {
#ifdef UARTE_PRESENT
    NRF_UARTE_Type *dev;    
#else
    NRF_UART_Type *dev;     
#endif
    gpio_t rx_pin;          
    gpio_t tx_pin;          
#ifdef MODULE_PERIPH_UART_HW_FC
    gpio_t rts_pin;         
    gpio_t cts_pin;         
#endif
    uint8_t irqn;           
} uart_conf_t;
 
#ifndef UART_TXBUF_SIZE
#define UART_TXBUF_SIZE    (64)
#endif
 
#define USBDEV_CPU_DMA_ALIGNMENT       (4)
 
#define USBDEV_CPU_DMA_REQUIREMENTS    __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
 
#if !defined(CPU_FAM_NRF51) && !defined(DOXYGEN)
#define PWM_CHANNELS        (4U)
 
#define PWM_MODE(ud, pol)   (ud | (pol << 15))
 
#define HAVE_PWM_MODE_T
typedef enum {
    PWM_LEFT       = PWM_MODE(0, 1),    
    PWM_RIGHT      = PWM_MODE(0, 0),    
    PWM_CENTER     = PWM_MODE(1, 1),    
    PWM_CENTER_INV = PWM_MODE(1, 0)     
} pwm_mode_t;
 
#if defined(PWM_PRESENT)
typedef struct {
    NRF_PWM_Type *dev;                  
    gpio_t pin[PWM_CHANNELS];           
} pwm_conf_t;
#endif
#endif /* ndef CPU_FAM_NRF51 */
#ifndef CPU_NRF51
 
#define SPI_SCKSEL          (dev(bus)->PSEL.SCK)    
#define SPI_MOSISEL         (dev(bus)->PSEL.MOSI)   
#define SPI_MISOSEL         (dev(bus)->PSEL.MISO)   
typedef struct {
    NRF_SPIM_Type *dev; 
    gpio_t sclk;        
    gpio_t mosi;        
    gpio_t miso;        
#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
    uint8_t ppi;        
#endif
} spi_conf_t;
 
typedef void (*shared_irq_cb_t)(void *arg);
 
void shared_irq_register_spi(NRF_SPIM_Type *bus,
                              shared_irq_cb_t cb, void *arg);
 
void shared_irq_register_i2c(NRF_TWIM_Type *bus,
                              shared_irq_cb_t cb, void *arg);
 
void shared_irq_register_uart(NRF_UARTE_Type *bus,
                              shared_irq_cb_t cb, void *arg);
 
void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg);
 
void nrf5x_i2c_release(NRF_TWIM_Type *bus);
 
void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg);
 
void nrf5x_spi_release(NRF_SPIM_Type *bus);
 
#ifndef UART_TXBUF_SIZE
#define UART_TXBUF_SIZE    (64)
#endif
 
#ifndef CONFIG_SPI_MBUF_SIZE
#define CONFIG_SPI_MBUF_SIZE    64
#endif
 
#ifndef DOXYGEN
#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       = 0xff,                         
    I2C_SPEED_NORMAL    = TWIM_FREQUENCY_FREQUENCY_K100,    
    I2C_SPEED_FAST      = TWIM_FREQUENCY_FREQUENCY_K400,    
    I2C_SPEED_FAST_PLUS = 0xfe,                         
    I2C_SPEED_HIGH      = 0xfd,                         
} i2c_speed_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    NRF_TWIM_Type *dev;         
    gpio_t scl;                 
    gpio_t sda;                 
    i2c_speed_t speed;          
} i2c_conf_t;
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_WRITE_REG
#define i2c_pin_sda(dev) i2c_config[dev].sda    
#define i2c_pin_scl(dev) i2c_config[dev].scl    
#endif /* ndef CPU_NRF51 */
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_COMMON_H */